1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
4 # Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
7 # https://www.qualcomm.com/products/qca4531
10 # - MIPS Processor ID (PRId): 0x00019374
11 # - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
12 # operating at up to 650 MHz
13 # - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
15 # - TRST is not available.
16 # - EJTAG PrRst signal is not supported
17 # - RESET_L pin B56 on the SoC will reset internal JTAG logic.
19 # Pins related for debug and bootstrap:
20 # Name Pin Description
22 # JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
23 # JTAG_TDI GPIO1, (B23) Software configurable, default JTAG
24 # JTAG_TDO GPIO2, (A28) Software configurable, default JTAG
25 # JTAG_TMS GPIO3, (A29) Software configurable, default JTAG
27 # RESET_L -, (B56) Input only
28 # SYS_RST_L GPIO17, (A79) Output reset request or GPIO
30 # JTAG_MODE GPIO16, (A78) 0 - JTAG (Default); 1 - EJTAG
31 # DDR_SELECT GPIO10, (A57) 0 - DDR2; 1 - DDR1
33 # UART0_SOUT GPIO10, (A57)
34 # UART0_SIN GPIO9, (B49)
36 # Per default we need to use "none" variant to be able properly "reset init"
37 # or "reset halt" the CPU.
38 reset_config none srst_pulls_trst
40 # For SRST based variant we still need proper timings.
41 # For ETH part the reset should be asserted at least for 10ms
42 # Since there is no other information let's take 100ms to be sure.
43 adapter srst pulse_width 100
45 # according to the SoC documentation it should take at least 5ms from
46 # reset end till bootstrap end. In the practice we need 8ms to get JTAG back
50 if { [info exists CHIPNAME] } {
51 set _CHIPNAME $_CHIPNAME
56 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
58 set _TARGETNAME $_CHIPNAME.cpu
59 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
61 # provide watchdog helper.
62 proc disable_watchdog { } {
66 $_TARGETNAME configure -event halted { disable_watchdog }
68 # Since PrRst is not supported and SRST will reset complete chip
69 # with JTAG engine, we need to reset CPU from CPU itself.
70 $_TARGETNAME configure -event reset-assert-pre {
74 $_TARGETNAME configure -event reset-assert {
75 catch "mww 0xb806001C 0x01000000"
78 # To be able to trigger complete chip reset, in case JTAG is blocked
79 # or CPU not responding, we still can use this helper.
81 reset_config srst_only
87 # Section with helpers which can be used by boards
88 proc qca4531_ddr2_550_550_init {} {
89 # Clear reset flags for different SoC components
90 mww 0xb806001c 0xfeceffff
91 mww 0xb806001c 0xeeceffff
92 mww 0xb806001c 0xe6ceffff
96 mww 0xb8116c40 0x633c8176
97 # Increase the DDR voltage
98 mww 0xb8116c44 0x10200000
100 mww 0xb81162c0 0x4b962100
102 mww 0xb81162c8 0x04000144
103 # Recommended PLL configurations
104 mww 0xb81161c4 0x54086000
105 mww 0xb8116244 0x54086000
108 mww 0xb8050008 0x0131001c
109 mww 0xb8050000 0x40001580
110 mww 0xb8050004 0x40015800
111 mww 0xb8050008 0x0131001c
112 mww 0xb8050000 0x00001580
113 mww 0xb8050004 0x00015800
114 mww 0xb8050008 0x01310000
115 mww 0xb8050044 0x781003ff
116 mww 0xb8050048 0x003c103f
119 mww 0xb8000108 0x401f0042
120 mww 0xb80000b8 0x0000166d
121 mww 0xb8000000 0xcfaaf33b
122 mww 0xb800015c 0x0000000f
123 mww 0xb8000004 0xa272efa8
124 mww 0xb8000018 0x0000ffff
125 mww 0xb80000c4 0x74444444
126 mww 0xb80000c8 0x00000444
127 mww 0xb8000004 0xa210ee28
128 mww 0xb8000004 0xa2b2e1a8
147 mww 0xb8000014 0x40be
150 mww 0xb80000cc 0xfffff
152 # UART GPIO programming
153 mww 0xb8040000 0xff30b
155 mww 0xb8040034 0x160000