3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
10 # Although the OMAP4430 supposedly has an ICEpick-D, only the
11 # ICEpick-C router commands seem to work.
12 # See http://processors.wiki.ti.com/index.php/ICEPICK
13 source [find target/icepick.cfg]
19 if { [info exists DAP_TAPID ] } {
20 set _DAP_TAPID $DAP_TAPID
22 set _DAP_TAPID 0x3BA00477
25 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
26 -expected-id $_DAP_TAPID -disable
27 jtag configure $_CHIPNAME.dap -event tap-enable \
28 "icepick_c_tapenable $_CHIPNAME.jrc 9"
32 # M3 DAPs, one per core
34 if { [info exists M3_DAP_TAPID ] } {
35 set _M3_DAP_TAPID $M3_DAP_TAPID
37 set _M3_DAP_TAPID 0x4BA00477
40 jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
41 -expected-id $_M3_DAP_TAPID -disable
42 jtag configure $_CHIPNAME.m31_dap -event tap-enable \
43 "icepick_c_tapenable $_CHIPNAME.jrc 5"
45 jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
46 -expected-id $_M3_DAP_TAPID -disable
47 jtag configure $_CHIPNAME.m30_dap -event tap-enable \
48 "icepick_c_tapenable $_CHIPNAME.jrc 4"
52 # ICEpick-D JRC (JTAG route controller)
54 if { [info exists JRC_TAPID ] } {
55 set _JRC_TAPID $JRC_TAPID
57 set _JRC_TAPID 0x3b95c02f
60 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
61 -expected-id $_JRC_TAPID
63 # Required by ICEpick to power-up the debug domain
64 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
68 # GDB target: Cortex-A9, using DAP
70 # The debugger can connect to either core of the A9, but currently
71 # not both simultaneously. Change -coreid to 1 to connect to the
74 set _TARGETNAME $_CHIPNAME.cpu
75 target create $_TARGETNAME cortex_a9 -chain-position $_CHIPNAME.dap -coreid 0
77 # SRAM: 56KiB at 0x4030.0000
78 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
82 # M3 targets, separate TAP/DAP for each core
84 target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
85 target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
88 # Once the JRC is up, enable our TAPs
89 jtag configure $_CHIPNAME.jrc -event setup "
90 jtag tapenable $_CHIPNAME.dap
91 jtag tapenable $_CHIPNAME.m30_dap
92 jtag tapenable $_CHIPNAME.m31_dap
95 proc omap4_dbginit {target} {
96 # General Cortex A9 debug initialisation
100 $_TARGETNAME configure -event reset-assert-post "omap4_dbginit $_TARGETNAME"
102 # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
103 # ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
104 set PRM_RSTCTRL 0x4A307B00
105 $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 0x1"