1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # script for Nordic nRF51 series, a Cortex-M0 chip
7 source [find target/swj-dp.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
15 if { [info exists ENDIAN] } {
21 # Work-area is a space in RAM used for flash programming
23 if { [info exists WORKAREASIZE] } {
24 set _WORKAREASIZE $WORKAREASIZE
26 set _WORKAREASIZE 0x4000
29 if { [info exists CPUTAPID] } {
30 set _CPUTAPID $CPUTAPID
32 set _CPUTAPID 0x0bb11477
35 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
36 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
38 set _TARGETNAME $_CHIPNAME.cpu
39 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
44 # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
45 cortex_m reset_config sysresetreq
48 flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
49 flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
52 # The chip should start up from internal 16Mhz RC, so setting adapter
53 # clock to 1Mhz should be OK
57 proc enable_all_ram {} {
58 # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
59 # are reliably enabled after reset on some revisions (contrary to spec.) So after
60 # resetting we enable all banks via the RAMON register
63 $_TARGETNAME configure -event reset-end { enable_all_ram }