1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
4 # Copyright (C) 2018 by Jean-Christian de Rivaz
5 # Based on NXP proposal https://community.nxp.com/message/1011149
6 # Many thanks to Dries Moors from NXP support.
9 source [find target/swj-dp.tcl]
10 source [find mem_helper.tcl]
12 if { [info exists CHIPNAME] } {
13 set _CHIPNAME $CHIPNAME
18 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
19 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
21 set _TARGETNAME $_CHIPNAME.cpu
22 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
24 # If srst is not fitted use SYSRESETREQ to perform a soft reset
25 cortex_m reset_config sysresetreq
27 adapter srst delay 100
29 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
31 flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
33 echo "*********************************************************************************"
34 echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
35 echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
36 echo "* unpowered. These modes can be entered by firmware. The default firmware image"
37 echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
38 echo "* during development, and only later add them when the functionality is complete."
39 echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
40 echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
41 echo "* signal to the chip RESETN pin and add the following in your configuration:"
42 echo "* reset_config srst_only; flash init; catch init; reset"
43 echo "* But if the actual firmware immediately set the power down mode after reset,"
44 echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
45 echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
46 echo "*********************************************************************************"
48 # Using soft-reset 'reset_config none' is strongly discouraged.
49 # RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
50 # Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
52 proc set_sysclk_500khz {} {
53 set SYSCLKCTRL 0x40048020
54 set SYSCLKUEN 0x40048024
56 mmw $SYSCLKCTRL 0x8 0xe
58 echo "Notice: sysclock set to 500kHz."
61 # Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
62 # Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
63 # Bit Symbol Value Description
64 # 0 map - interrupt vector remap. 0 after boot.
65 # 0 interrupt vector reside in Flash
66 # 1 interrupt vector reside in SRAM
67 # 5:1 offset - system memory remap offset. 00000b after boot.
68 # 00000b interrupt vectors in flash or remapped to SRAM but no offset
70 # 00111b interrupt vectors offset in flash or SRAM to 1K word segment
72 # 11111b interrupt vectors offset in flash to 1K word segment 8 to 31
75 proc set_no_remap {} {
77 echo "Notice: interrupt vector set to no remap."
80 $_TARGETNAME configure -event reset-init {