1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
18 if { [info exists M4_JTAG_TAPID] } {
19 set _M4_JTAG_TAPID $M4_JTAG_TAPID
21 set _M4_JTAG_TAPID 0x4ba00477
27 if { [info exists M4_SWD_TAPID] } {
28 set _M4_SWD_TAPID $M4_SWD_TAPID
30 set _M4_SWD_TAPID 0x2ba01477
33 source [find target/swj-dp.tcl]
36 set _M4_TAPID $_M4_JTAG_TAPID
38 set _M4_TAPID $_M4_SWD_TAPID
44 if { [info exists M0_JTAG_TAPID] } {
45 set _M0_JTAG_TAPID $M0_JTAG_TAPID
47 set _M0_JTAG_TAPID 0x0ba01477
50 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
51 -expected-id $_M4_TAPID
52 dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
53 target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
55 # LPC4370 has 96+32 KB contiguous SRAM
56 if { [info exists WORKAREASIZE] } {
57 set _WORKAREASIZE $WORKAREASIZE
59 set _WORKAREASIZE 0x20000
61 $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
62 -work-area-size $_WORKAREASIZE -work-area-backup 0
65 jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
66 -expected-id $_M0_JTAG_TAPID
67 jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
68 -expected-id $_M0_JTAG_TAPID
70 dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
71 dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
72 target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
73 target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
76 $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
77 -work-area-size 0x92000 -work-area-backup 0
79 # 16+2 KB M0 subsystem SRAM
80 $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
81 -work-area-size 0x4800 -work-area-backup 0
83 # Default to the Cortex-M4
88 cortex_m reset_config vectreset