1 # SPDX-License-Identifier: GPL-2.0-or-later
3 source [find target/swj-dp.tcl]
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
16 if { [info exists M4_JTAG_TAPID] } {
17 set _M4_JTAG_TAPID $M4_JTAG_TAPID
19 set _M4_JTAG_TAPID 0x4ba00477
25 if { [info exists M4_SWD_TAPID] } {
26 set _M4_SWD_TAPID $M4_SWD_TAPID
28 set _M4_SWD_TAPID 0x2ba01477
32 set _M4_TAPID $_M4_JTAG_TAPID
34 set _M4_TAPID $_M4_SWD_TAPID
40 if { [info exists M0_JTAG_TAPID] } {
41 set _M0_JTAG_TAPID $M0_JTAG_TAPID
43 set _M0_JTAG_TAPID 0x0ba01477
46 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
47 -expected-id $_M4_TAPID
48 dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
49 target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
52 swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
53 -expected-id $_M0_JTAG_TAPID
54 dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
55 target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
58 # LPC4350 has 96+32 KB SRAM
59 if { [info exists WORKAREASIZE] } {
60 set _WORKAREASIZE $WORKAREASIZE
62 set _WORKAREASIZE 0x20000
64 $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
65 -work-area-size $_WORKAREASIZE -work-area-backup 0
68 # on this CPU we should use VECTRESET to perform a soft reset and
69 # manually reset the periphery
70 # SRST or SYSRESETREQ disable the debug interface for the time of
71 # the reset and will not fit our requirements for a consistent debug
73 cortex_m reset_config vectreset