1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # configuration file for NXP i.MX8M family of SoCs
6 if { [info exists CHIPNAME] } {
7 set _CHIPNAME $CHIPNAME
12 if { [info exists CHIPCORES] } {
18 # CoreSight Debug Access Port
19 if { [info exists DAP_TAPID] } {
20 set _DAP_TAPID $DAP_TAPID
22 set _DAP_TAPID 0x5ba00477
26 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
27 -expected-id $_DAP_TAPID
29 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
31 set _TARGETNAME $_CHIPNAME.a53
32 set _CTINAME $_CHIPNAME.cti
34 set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
35 set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
37 for { set _core 0 } { $_core < $_cores } { incr _core } {
39 cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
40 -baseaddr [lindex $CTIBASE $_core]
42 set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
43 -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
46 # non-boot core examination may fail
47 set _command "$_command -defer-examine"
48 set _smp_command "$_smp_command $_TARGETNAME.$_core"
50 set _command "$_command -rtos hwthread"
51 set _smp_command "target smp $_TARGETNAME.$_core"
59 # declare the auxiliary Cortex-M4 core on AP #4
60 target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
63 # AHB-AP for direct access to soc bus
64 target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
66 # default target is A53 core 0
67 targets $_TARGETNAME.0