5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 # 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9
12 if { [info exists DAP_TAPID] } {
13 set _DAP_TAPID $DAP_TAPID
15 set _DAP_TAPID 0x4ba00477
18 jtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \
19 -expected-id $_DAP_TAPID
20 dap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4
22 jtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \
23 -expected-id $_DAP_TAPID
24 dap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9
27 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
29 # System JTAG Controller
30 if { [info exists SJC_TAPID] } {
31 set _SJC_TAPID $SJC_TAPID
33 set _SJC_TAPID 0x0891c01d
35 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
36 -expected-id $_SJC_TAPID -ignore-version
38 # Cortex-A9 (boot core)
39 target create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \
40 -coreid 0 -dbgbase 0x82150000
42 # Cortex-M4 (default off)
43 target create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \
44 -ap-num 0 -defer-examine
47 target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0
49 # Default target is Cortex-A9
50 targets $_CHIPNAME.cpu_a9