2 # Freescale i.MX6 series
4 # Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL
6 # Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
15 # CoreSight Debug Access Port
16 if { [info exists DAP_TAPID] } {
17 set _DAP_TAPID $DAP_TAPID
19 set _DAP_TAPID 0x4ba00477
22 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
23 -expected-id $_DAP_TAPID
26 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
28 # System JTAG Controller
30 # List supported SJC TAPIDs from imx reference manuals:
31 set _SJC_TAPID_6Q 0x0191c01d
32 set _SJC_TAPID_6D 0x0191e01d
33 set _SJC_TAPID_6QP 0x3191c01d
34 set _SJC_TAPID_6DP 0x3191d01d
35 set _SJC_TAPID_6DL 0x0891a01d
36 set _SJC_TAPID_6S 0x0891b01d
37 set _SJC_TAPID_6SL 0x0891f01d
38 set _SJC_TAPID_6SLL 0x088c201d
40 # Allow external override of the first SJC TAPID
41 if { [info exists SJC_TAPID] } {
42 set _SJC_TAPID $SJC_TAPID
44 set _SJC_TAPID $_SJC_TAPID_6Q
47 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
49 -expected-id $_SJC_TAPID \
50 -expected-id $_SJC_TAPID_6QP \
51 -expected-id $_SJC_TAPID_6DP \
52 -expected-id $_SJC_TAPID_6D \
53 -expected-id $_SJC_TAPID_6DL \
54 -expected-id $_SJC_TAPID_6S \
55 -expected-id $_SJC_TAPID_6SL \
56 -expected-id $_SJC_TAPID_6SLL
58 # GDB target: Cortex-A9, using DAP, configuring only one core
59 # Base addresses of cores:
64 set _TARGETNAME $_CHIPNAME.cpu.0
65 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
66 target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
67 -coreid 0 -dbgbase 0x82150000
69 # some TCK cycles are required to activate the DEBUG power domain
70 jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
72 proc imx6_dbginit {target} {
73 # General Cortex-A8/A9 debug initialisation
77 # Slow speed to be sure it will work
79 $_TARGETNAME configure -event reset-start { adapter speed 1000 }
81 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"