1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Support for General Plus GP326XXXA chips
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
10 set _CHIPNAME gp326xxxa
13 if { [info exists ENDIAN] } {
19 if { [info exists CPUTAPID] } {
20 set _CPUTAPID $CPUTAPID
22 set _CPUTAPID 0x4f1f0f0f
25 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
27 set _TARGETNAME $_CHIPNAME.cpu
29 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
31 # Use internal SRAM as a work area
32 $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
34 # The chip has both lines connected together
35 reset_config trst_and_srst srst_pulls_trst
36 # This delay is needed otherwise communication with the target would
38 adapter srst delay 100
40 # Set the adapter speed ridiculously low just in case we are
41 # running off of a 32kHz clock
44 proc gp32xxxa_halt_and_reset_control_registers {} {
45 # System control registers
46 set P_SYSTEM_CTRL_NEW 0xD0000008
47 set P_SYSTEM_CTRL 0xD000000C
48 set P_SYSTEM_CLK_EN0 0xD0000010
49 set P_SYSTEM_CLK_EN1 0xD0000014
50 set P_SYSTEM_RESET_FLAG 0xD0000018
51 set P_SYSTEM_CLK_CTRL 0xD000001C
52 set P_SYSTEM_LVR_CTRL 0xD0000020
53 set P_SYSTEM_WATCHDOG_CTRL 0xD0000024
54 set P_SYSTEM_PLLEN 0xD000005C
56 # Since we can't use SRST without pulling TRST
57 # we can't assume the state of the clock configuration
58 # or watchdog settings. So reset them before porceeding
60 # Set the adapter speed ridiculously low just in case we are
61 # running off of a 32kHz clock
64 # Disable any advanced features at this stage
65 arm7_9 dcc_downloads disable
66 arm7_9 fast_memory_access disable
70 # Reset all system control registers to their default "after-reset" values
71 mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000
72 mwh $P_SYSTEM_LVR_CTRL 0x0000
74 mwh $P_SYSTEM_CTRL_NEW 0x0001
75 mwh $P_SYSTEM_CTRL 0x0001
76 # Clear all reset flags by writing 1's
77 mwh $P_SYSTEM_RESET_FLAG 0x001C
79 mwh $P_SYSTEM_CLK_CTRL 0x8000
80 mwh $P_SYSTEM_CLK_EN0 0xFFFF
81 mwh $P_SYSTEM_CLK_EN1 0xFFFF
82 mwh $P_SYSTEM_PLLEN 0x0010
84 # Unfortunately there's no register that would allow us to
85 # know if PLL is locked. So just wait for 100ms in hopes that
89 # Now that we know that we are running at 48Mhz
90 # Increase JTAG speed and enable speed optimization features
92 arm7_9 dcc_downloads enable
93 arm7_9 fast_memory_access enable
96 $_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }