2 # GigaDevice GD32VF103 target
4 # https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
7 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME gd32vf103
17 # The smallest RAM size 6kB (GD32VF103C4/T4/R4)
18 if { [info exists WORKAREASIZE] } {
19 set _WORKAREASIZE $WORKAREASIZE
21 set _WORKAREASIZE 0x1800
24 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
26 set _TARGETNAME $_CHIPNAME.cpu
27 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
29 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
31 set _FLASHNAME $_CHIPNAME.flash
32 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
34 # DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU
35 # does not allow the debugger to access memory.
36 # Stop watchdogs at least before flash programming.
37 $_TARGETNAME configure -event reset-init {
38 # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
39 mmw 0xE0042004 0x00000300 0