1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # GigaDevice GD32VF103 target
6 # https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
9 source [find mem_helper.tcl]
13 if { [info exists CHIPNAME] } {
14 set _CHIPNAME $CHIPNAME
16 set _CHIPNAME gd32vf103
19 # The smallest RAM size 6kB (GD32VF103C4/T4/R4)
20 if { [info exists WORKAREASIZE] } {
21 set _WORKAREASIZE $WORKAREASIZE
23 set _WORKAREASIZE 0x1800
26 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
28 set _TARGETNAME $_CHIPNAME.cpu
29 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
31 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
33 set _FLASHNAME $_CHIPNAME.flash
34 flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
36 # DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU
37 # does not allow the debugger to access memory.
38 # Stop watchdogs at least before flash programming.
39 $_TARGETNAME configure -event reset-init {
40 # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
41 mmw 0xE0042004 0x00000300 0