3 echo "List of useful functions for C100 processor:"
4 echo "1) reset init: will set up your Telo board"
5 echo "2) setupNOR: will setup NOR access"
6 echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
7 echo "4) setupGPIO: will setup GPIOs for Telo board"
8 echo "5) showGPIO: will show current GPIO config registers"
9 echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
10 echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
11 echo "8) showAmbaClk: will show current config registers for Amba Bus Clock"
12 echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
13 echo "10) showArmClk: will show current config registers for Arm Bus Clock"
14 echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
15 echo "12) ooma_board_detect: will show which version of Telo you have"
16 echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
17 echo "14) showDDR2: will show DDR2 config registers"
18 echo "15) showWatchdog: will show current register config for watchdog"
19 echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
20 echo "17) bootNOR: will boot Telo from NOR"
21 echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
22 echo "19) putcUART0: will print a character on UART0"
23 echo "20) putsUART0: will print a string on UART0"
24 echo "21) trainDDR2: will run DDR2 training program"
25 echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
28 source [find mem_helper.tcl]
30 # read a 64-bit register (memory mapped)
32 return [read_memory $reg 32 2]
36 # write a 64-bit register (memory mapped)
37 proc mw64bit {reg value} {
38 set high [expr {$value >> 32}]
39 set low [expr {$value & 0xffffffff}]
40 #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
42 mww [expr {$reg+4}] $high
47 echo "This is the current NOR setup"
48 set EX_CSEN_REG [regs EX_CSEN_REG ]
49 set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
50 set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
51 set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
52 set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
53 set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
54 set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
55 set EX_MFSM_REG [regs EX_MFSM_REG ]
56 set EX_CSFSM_REG [regs EX_CSFSM_REG ]
57 set EX_WRFSM_REG [regs EX_WRFSM_REG ]
58 set EX_RDFSM_REG [regs EX_RDFSM_REG ]
60 echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
61 echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
62 echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
63 echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
64 echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
65 echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
66 echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
67 echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
68 echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
69 echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
70 echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
76 echo "This is the current GPIO register setup"
77 # GPIO outputs register
78 set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
79 # GPIO Output Enable register
80 set GPIO_OE_REG [regs GPIO_OE_REG]
81 set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
82 set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
84 set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
85 set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
86 set MUX_CONF_REG [regs MUX_CONF_REG]
87 set SYSCONF_REG [regs SYSCONF_REG]
88 set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
89 set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
90 set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
91 set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
92 set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
94 echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
95 echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
96 echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
97 echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
98 echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
99 echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
100 echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
101 echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
102 echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
103 echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
104 echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
105 echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
106 echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
111 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
112 proc showAmbaClk {} {
113 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
114 set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
115 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
117 echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
118 set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
119 # see if the PLL is in bypass mode
120 set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
121 echo [format "PLL bypass bit: %d" $bypass]
123 echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
125 # nope, extract x,y,w and compute the PLL output freq.
126 set x [expr {($value & 0x0001F0000) >> 16}]
127 echo [format "x: %d" $x]
128 set y [expr {($value & 0x00000007F)}]
129 echo [format "y: %d" $y]
130 set w [expr {($value & 0x000000300) >> 8}]
131 echo [format "w: %d" $w]
132 echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
137 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
138 # this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
139 proc setupAmbaClk {} {
140 set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
141 set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
142 set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
143 set ARM_AHB_BYP [regs ARM_AHB_BYP]
144 set PLL_DISABLE [regs PLL_DISABLE]
145 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
146 set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
147 set DIV_BYPASS [regs DIV_BYPASS]
148 set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
149 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
150 set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
151 set w [config w_amba]
152 set x [config x_amba]
153 set y [config y_amba]
155 echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
156 #echo [format "setupAmbaClk: w= %d" $w]
157 #echo [format "setupAmbaClk: x= %d" $x]
158 #echo [format "setupAmbaClk: y= %d" $y]
159 # set PLL into BYPASS mode using MUX
160 mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
161 # do an internal PLL bypass
162 mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
163 # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
164 # openocd smallest resolution is 1ms so, wait 1ms
167 mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
171 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
174 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
175 mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
176 # wait for PLL to lock
177 echo "Waiting for Amba PLL to lock"
178 while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
179 # remove the internal PLL bypass
180 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
181 # remove PLL from BYPASS mode using MUX
182 mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
186 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
188 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
189 set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
190 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
192 echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
193 set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
194 # see if the PLL is in bypass mode
195 set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
196 echo [format "PLL bypass bit: %d" $bypass]
198 echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
200 # nope, extract x,y,w and compute the PLL output freq.
201 set x [expr {($value & 0x0001F0000) >> 16}]
202 echo [format "x: %d" $x]
203 set y [expr {($value & 0x00000007F)}]
204 echo [format "y: %d" $y]
205 set w [expr {($value & 0x000000300) >> 8}]
206 echo [format "w: %d" $w]
207 echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
211 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
212 # Arm Clock is used by two ARM1136 cores
213 proc setupArmClk {} {
214 set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
215 set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
216 set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
217 set ARM_AHB_BYP [regs ARM_AHB_BYP]
218 set PLL_DISABLE [regs PLL_DISABLE]
219 set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
220 set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
221 set DIV_BYPASS [regs DIV_BYPASS]
222 set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
223 set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
224 set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
229 echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
230 #echo [format "setupArmClk: w= %d" $w]
231 #echo [format "setupArmaClk: x= %d" $x]
232 #echo [format "setupArmaClk: y= %d" $y]
233 # set PLL into BYPASS mode using MUX
234 mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
235 # do an internal PLL bypass
236 mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
237 # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
238 # openocd smallest resolution is 1ms so, wait 1ms
241 mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
245 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
248 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
249 mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
250 # wait for PLL to lock
251 echo "Waiting for Amba PLL to lock"
252 while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
253 # remove the internal PLL bypass
254 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
255 # remove PLL from BYPASS mode using MUX
256 mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
267 # converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
269 echo "Configuring DDR2"
271 set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
272 set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
273 set MEMORY_CR [regs MEMORY_CR]
274 set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
275 set DDR_RST [regs DDR_RST]
277 # put DDR controller in reset (so that it is reset and correctly configured)
278 # this is only necessary if DDR was previously confiured
280 mmw $BLOCK_RESET_REG 0x0 $DDR_RST
282 set M [expr {1024 * 1024}]
283 set DDR_SZ_1024M [expr {1024 * $M}]
284 set DDR_SZ_256M [expr {256 * $M}]
285 set DDR_SZ_128M [expr {128 * $M}]
286 set DDR_SZ_64M [expr {64 * $M}]
287 # ooma_board_detect returns DDR2 memory size
288 set tmp [ooma_board_detect]
289 if {$tmp == "128M"} {
290 echo "DDR2 size 128MB"
291 set ddr_size $DDR_SZ_128M
292 } elseif {$tmp == "256M"} {
293 echo "DDR2 size 256MB"
294 set ddr_size $DDR_SZ_256M
296 echo "Don't know how to handle this DDR2 size?"
299 # Memory setup register
300 mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
303 # Take DDR controller out of reset
304 mmw $BLOCK_RESET_REG $DDR_RST 0x0
308 # This will setup Denali DDR2 controller
309 if {$tmp == "128M"} {
310 configureDDR2regs_128M
311 } elseif {$tmp == "256M"} {
312 configureDDR2regs_256M
314 echo "Don't know how to configure DDR2 setup?"
322 set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
323 set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
324 set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
325 set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
326 set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
327 set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
328 set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
329 set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
330 set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
331 set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
332 set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
333 set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
334 set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
335 set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
336 set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
337 set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
338 set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
339 set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
340 set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
341 set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
342 set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
344 set tmp [mr64bit $DENALI_CTL_00_DATA]
345 echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
346 set tmp [mr64bit $DENALI_CTL_01_DATA]
347 echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
348 set tmp [mr64bit $DENALI_CTL_02_DATA]
349 echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
350 set tmp [mr64bit $DENALI_CTL_03_DATA]
351 echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
352 set tmp [mr64bit $DENALI_CTL_04_DATA]
353 echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
354 set tmp [mr64bit $DENALI_CTL_05_DATA]
355 echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
356 set tmp [mr64bit $DENALI_CTL_06_DATA]
357 echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
358 set tmp [mr64bit $DENALI_CTL_07_DATA]
359 echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
360 set tmp [mr64bit $DENALI_CTL_08_DATA]
361 echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
362 set tmp [mr64bit $DENALI_CTL_09_DATA]
363 echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
364 set tmp [mr64bit $DENALI_CTL_10_DATA]
365 echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
366 set tmp [mr64bit $DENALI_CTL_11_DATA]
367 echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
368 set tmp [mr64bit $DENALI_CTL_12_DATA]
369 echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
370 set tmp [mr64bit $DENALI_CTL_13_DATA]
371 echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
372 set tmp [mr64bit $DENALI_CTL_14_DATA]
373 echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
374 set tmp [mr64bit $DENALI_CTL_15_DATA]
375 echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
376 set tmp [mr64bit $DENALI_CTL_16_DATA]
377 echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
378 set tmp [mr64bit $DENALI_CTL_17_DATA]
379 echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
380 set tmp [mr64bit $DENALI_CTL_18_DATA]
381 echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
382 set tmp [mr64bit $DENALI_CTL_19_DATA]
383 echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
384 set tmp [mr64bit $DENALI_CTL_20_DATA]
385 echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
390 # this follows u-boot/cpu/arm1136/start.S
391 set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
392 set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
393 set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
394 set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
395 set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
396 set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
397 set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
398 set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
399 set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
400 set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
401 set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
402 set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
403 set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
404 set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
405 set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
408 # unlock writing to IOCTRL register
409 mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
410 # enable address lines A15-A21
411 mmw $GPIO_IOCTRL_REG 0xf 0x0
412 # set ARM into supervisor mode (SVC32)
414 # Do I need this in JTAG mode?
415 # it really should be done as 'and ~0x1f | 0xd3 but
416 # openocd does not support this yet
419 # * flush v4 I/D caches
422 # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
423 arm mcr 15 0 7 7 0 0x0
424 # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
425 arm mcr 15 0 8 7 0 0x0
428 # * disable MMU stuff and caches
430 # mrc p15, 0, r0, c1, c0, 0
432 # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
433 # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
434 # orr r0, r0, #0x00000002 @ set bit 2 (A) Align
435 # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
436 # orr r0, r0, #0x00400000 @ set bit 22 (U)
437 # mcr p15, 0, r0, c1, c0, 0
438 arm mcr 15 0 1 0 0 0x401002
439 # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
441 # // Setting APB Bus Wait states to 1, set post write
442 # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
443 mww $APB_ACCESS_WS_REG 0x40
445 # // enable all 6 masters for ARAM
446 mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
447 # // enable all 6 masters for EBUS
448 mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
451 # // disable pipeline mode in ARAM
452 # I don't think this is documented anywhere?
453 mww $INTC_ARM1_CONTROL_REG 0x1
456 # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
459 # ? (u-boot does nothing here)
462 putsUART0 "C100 initialization complete.\n"
463 echo "C100 initialization complete."
466 # show current state of watchdog timer
467 proc showWatchdog {} {
468 set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
469 set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
470 set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
472 echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
473 echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
474 echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
477 # converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
478 # this will trigger watchdog reset
479 # the sw. reset does not work on C100
480 # watchdog reset effectively works as hw. reset
482 set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
483 set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
484 set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
486 # allow the counter to count to high value before triggering
487 # this is because register writes are slow over JTAG and
488 # I don't want to miss the high_bound==curr_count condition
489 mww $TIMER_WDT_HIGH_BOUND 0xffffff
490 mww $TIMER_WDT_CURRENT_COUNT 0x0
491 echo "JTAG speed lowered to 100kHz"
493 mww $TIMER_WDT_CONTROL 0x1
494 # wait until the reset
495 echo -n "Waiting for watchdog to trigger..."
496 #while {[mrw $TIMER_WDT_CONTROL] == 1} {
497 # echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
501 while {[c100.cpu curstate] != "running"} { sleep 1}
503 echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]