2 # bluenrg-1/2 and bluenrg-lp devices support only SWD transports.
5 source [find target/swj-dp.tcl]
6 source [find mem_helper.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
11 set _CHIPNAME bluenrg-1
16 # Work-area is a space in RAM used for flash programming
17 # By default use 24kB-256bytes
18 if { [info exists WORKAREASIZE] } {
19 set _WORKAREASIZE $WORKAREASIZE
21 set _WORKAREASIZE 0x5F00
26 swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
27 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
29 set _TARGETNAME $_CHIPNAME.cpu
33 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
35 $_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0
37 # flash size will be probed
38 set _FLASHNAME $_CHIPNAME.flash
39 flash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME
41 # In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none
45 # if srst is not fitted use SYSRESETREQ to
46 # perform a soft reset
47 cortex_m reset_config sysresetreq
50 set JTAG_IDCODE_B2 0x0200A041
51 set JTAG_IDCODE_B1 0x0
53 $_TARGETNAME configure -event halted {
56 set _JTAG_IDCODE [mrw 0x40000004]
57 if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
58 # Stop watchdog during halt, if enabled. Only Bluenrg-1/2
59 set WDOG_VALUE [mrw 0x40700008]
60 if [expr {$WDOG_VALUE & (1 << 1)}] {
62 mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}]
66 $_TARGETNAME configure -event resumed {
69 set _JTAG_IDCODE [mrw 0x40000004]
70 if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {
71 if {$WDOG_VALUE_SET} {
72 # Restore watchdog enable value after resume. Only Bluenrg-1/2
73 mww 0x40700008 $WDOG_VALUE