1 # ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
2 # The chips are very similar; the SAMV series just has
3 # more peripherals and seems like the "flagship" of the
4 # family. This script will work for all of them.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
14 if { [info exists ENDIAN] } {
20 # Work-area is a space in RAM used for flash programming
22 if { [info exists WORKAREASIZE] } {
23 set _WORKAREASIZE $WORKAREASIZE
25 set _WORKAREASIZE 0x4000
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
31 set _CPUTAPID 0x0bd11477
34 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
35 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
37 set _TARGETNAME $_CHIPNAME.cpu
38 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
40 $_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
45 # if srst is not fitted use SYSRESETREQ to
46 # perform a soft reset
47 cortex_m reset_config sysresetreq
49 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
50 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
51 # makes the data access cacheable. This allows reading and writing data in the
52 # CPU cache from the debugger, which is far more useful than going straight to
53 # RAM when operating on typical variables, and is generally no worse when
54 # operating on special memory locations.
55 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
58 set _FLASHNAME $_CHIPNAME.flash
59 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME