1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Atheros AR71xx MIPS 24Kc SoC.
4 # tested on PB44 refererence board
9 reset_config trst_and_srst
13 jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
15 set _TARGETNAME $CHIPNAME.cpu
16 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
18 $_TARGETNAME configure -event reset-halt-post {
19 #setup PLL to lowest common denominator 300/300/150 setting
20 mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0
21 mww 0xb8050000 0x800f40a3 ;# send to PLL
23 #next command will reset for PLL changes to take effect
24 mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC)
27 $_TARGETNAME configure -event reset-init {
28 #complete pll initialization
29 mww 0xb8050000 0x800f0080 ;# set sw_update bit
30 mww 0xb8050008 0 ;# clear reset_switch bit
31 mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass
32 mww 0xb8050008 1 ;# set clock_switch bit
33 sleep 1 ;# wait for lock
35 # Setup DDR config and flash mapping
36 mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0)
37 mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
39 mww 0xb8000010 8 ;# force precharge all banks
40 mww 0xb8000010 1 ;# force EMRS update cycle
41 mww 0xb800000c 0 ;# clr ext. mode register
42 mww 0xb8000010 2 ;# force auto refresh all banks
43 mww 0xb8000010 8 ;# force precharge all banks
44 mww 0xb8000008 0x31 ;# set DDR mode value CAS=3
45 mww 0xb8000010 1 ;# force EMRS update cycle
46 mww 0xb8000014 0x461b ;# DDR refresh value
47 mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff)
48 mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7)
54 # setup working area somewhere in RAM
55 $_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
57 # serial SPI capable flash
58 # flash bank <driver> <base> <size> <chip_width> <bus_width>