git.gag.com Git - fw/openocd/blob - tcl/target/am437x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 source [find target/icepick.cfg]
   4 source [find mem_helper.tcl]
   5
   6 ###############################################################################
   7 ##                              AM437x Registers                             ##
   8 ###############################################################################
   9 set  PRCM_BASE_ADDR                  0x44df0000
  10 set  REVISION_PRM                    [expr       {$PRCM_BASE_ADDR     +  0x0000}]
  11 set  PRM_IRQSTATUS_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0004}]
  12 set  PRM_IRQENABLE_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0008}]
  13 set  PRM_IRQSTATUS_M3                [expr       {$PRCM_BASE_ADDR     +  0x000c}]
  14 set  PRM_IRQENABLE_M3                [expr       {$PRCM_BASE_ADDR     +  0x0010}]
  15 set  PM_MPU_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0300}]
  16 set  PM_MPU_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0304}]
  17 set  RM_MPU_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0314}]
  18 set  RM_MPU_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0324}]
  19 set  PM_GFX_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0400}]
  20 set  PM_GFX_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0404}]
  21 set  RM_GFX_RSTCTRL                  [expr       {$PRCM_BASE_ADDR     +  0x0410}]
  22 set  RM_GFX_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0414}]
  23 set  RM_GFX_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0424}]
  24 set  RM_RTC_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0524}]
  25 set  RM_WKUP_RSTCTRL                 [expr       {$PRCM_BASE_ADDR     +  0x2010}]
  26 set  RM_WKUP_RSTST                   [expr       {$PRCM_BASE_ADDR     +  0x2014}]
  27 set  CM_L3_AON_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x2800}]
  28 set  CM_WKUP_DEBUGSS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2820}]
  29 set  CM_L3S_TSC_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2900}]
  30 set  CM_WKUP_ADC_TSC_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2920}]
  31 set  CM_L4_WKUP_AON_CLKSTCTRL        [expr       {$PRCM_BASE_ADDR     +  0x2a00}]
  32 set  CM_WKUP_L4WKUP_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2a20}]
  33 set  CM_WKUP_WKUP_M3_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a28}]
  34 set  CM_WKUP_SYNCTIMER_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a30}]
  35 set  CM_WKUP_CLKDIV32K_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a38}]
  36 set  CM_WKUP_USBPHY0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a40}]
  37 set  CM_WKUP_USBPHY1_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a48}]
  38 set  CM_WKUP_CLKSTCTRL               [expr       {$PRCM_BASE_ADDR     +  0x2b00}]
  39 set  CM_WKUP_TIMER0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b20}]
  40 set  CM_WKUP_TIMER1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b28}]
  41 set  CM_WKUP_WDT0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b30}]
  42 set  CM_WKUP_WDT1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b38}]
  43 set  CM_WKUP_I2C0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b40}]
  44 set  CM_WKUP_UART0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b48}]
  45 set  CM_WKUP_SMARTREFLEX0_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b50}]
  46 set  CM_WKUP_SMARTREFLEX1_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b58}]
  47 set  CM_WKUP_CONTROL_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2b60}]
  48 set  CM_WKUP_GPIO0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b68}]
  49 set  CM_CLKMODE_DPLL_CORE            [expr       {$PRCM_BASE_ADDR     +  0x2d20}]
  50 set  CM_IDLEST_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d24}]
  51 set  CM_CLKSEL_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d2c}]
  52 set  CM_DIV_M4_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d38}]
  53 set  CM_DIV_M5_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d3c}]
  54 set  CM_DIV_M6_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d40}]
  55 set  CM_SSC_DELTAMSTEP_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d48}]
  56 set  CM_SSC_MODFREQDIV_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d4c}]
  57 set  CM_CLKMODE_DPLL_MPU             [expr       {$PRCM_BASE_ADDR     +  0x2d60}]
  58 set  CM_IDLEST_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d64}]
  59 set  CM_CLKSEL_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d6c}]
  60 set  CM_DIV_M2_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d70}]
  61 set  CM_SSC_DELTAMSTEP_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d88}]
  62 set  CM_SSC_MODFREQDIV_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d8c}]
  63 set  CM_CLKMODE_DPLL_DDR             [expr       {$PRCM_BASE_ADDR     +  0x2da0}]
  64 set  CM_IDLEST_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2da4}]
  65 set  CM_CLKSEL_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2dac}]
  66 set  CM_DIV_M2_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db0}]
  67 set  CM_DIV_M4_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db8}]
  68 set  CM_SSC_DELTAMSTEP_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dc8}]
  69 set  CM_SSC_MODFREQDIV_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dcc}]
  70 set  CM_CLKMODE_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2de0}]
  71 set  CM_IDLEST_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2de4}]
  72 set  CM_CLKSEL_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2dec}]
  73 set  CM_DIV_M2_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2df0}]
  74 set  CM_CLKSEL2_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2e04}]
  75 set  CM_SSC_DELTAMSTEP_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e08}]
  76 set  CM_SSC_MODFREQDIV_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e0c}]
  77 set  CM_CLKDCOLDO_DPLL_PER           [expr       {$PRCM_BASE_ADDR     +  0x2e14}]
  78 set  CM_CLKMODE_DPLL_DISP            [expr       {$PRCM_BASE_ADDR     +  0x2e20}]
  79 set  CM_IDLEST_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e24}]
  80 set  CM_CLKSEL_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e2c}]
  81 set  CM_DIV_M2_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e30}]
  82 set  CM_SSC_DELTAMSTEP_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e48}]
  83 set  CM_SSC_MODFREQDIV_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e4c}]
  84 set  CM_CLKMODE_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e60}]
  85 set  CM_IDLEST_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e64}]
  86 set  CM_CLKSEL_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e6c}]
  87 set  CM_DIV_M2_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e70}]
  88 set  CM_CLKSEL2_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e84}]
  89 set  CM_SSC_DELTAMSTEP_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e88}]
  90 set  CM_SSC_MODFREQDIV_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e8c}]
  91 set  CM_SHADOW_FREQ_CONFIG1          [expr       {$PRCM_BASE_ADDR     +  0x2fa0}]
  92 set  CM_SHADOW_FREQ_CONFIG2          [expr       {$PRCM_BASE_ADDR     +  0x2fa4}]
  93 set  CM_CLKOUT1_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4100}]
  94 set  CM_DLL_CTRL                     [expr       {$PRCM_BASE_ADDR     +  0x4104}]
  95 set  CM_CLKOUT2_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4108}]
  96 set  CLKSEL_TIMER1MS_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4200}]
  97 set  CLKSEL_TIMER2_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4204}]
  98 set  CLKSEL_TIMER3_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4208}]
  99 set  CLKSEL_TIMER4_CLK               [expr       {$PRCM_BASE_ADDR     +  0x420c}]
 100 set  CLKSEL_TIMER5_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4210}]
 101 set  CLKSEL_TIMER6_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4214}]
 102 set  CLKSEL_TIMER7_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4218}]
 103 set  CLKSEL_TIMER8_CLK               [expr       {$PRCM_BASE_ADDR     +  0x421c}]
 104 set  CLKSEL_TIMER9_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4220}]
 105 set  CLKSEL_TIMER10_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4224}]
 106 set  CLKSEL_TIMER11_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4228}]
 107 set  CLKSEL_WDT1_CLK                 [expr       {$PRCM_BASE_ADDR     +  0x422c}]
 108 set  CLKSEL_SYNCTIMER_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4230}]
 109 set  CLKSEL_MAC_CLK                  [expr       {$PRCM_BASE_ADDR     +  0x4234}]
 110 set  CLKSEL_CPTS_RFT_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4238}]
 111 set  CLKSEL_GFX_FCLK                 [expr       {$PRCM_BASE_ADDR     +  0x423c}]
 112 set  CLKSEL_GPIO0_DBCLK              [expr       {$PRCM_BASE_ADDR     +  0x4240}]
 113 set  CLKSEL_LCDC_PIXEL_CLK           [expr       {$PRCM_BASE_ADDR     +  0x4244}]
 114 set  CLKSEL_ICSS_OCP_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4248}]
 115 set  CLKSEL_DLL_AGING_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4250}]
 116 set  CLKSEL_USBPHY32KHZ_GCLK         [expr       {$PRCM_BASE_ADDR     +  0x4260}]
 117 set  CM_MPU_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8300}]
 118 set  CM_MPU_MPU_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8320}]
 119 set  CM_GFX_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8400}]
 120 set  CM_GFX_GFX_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8420}]
 121 set  CM_RTC_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8500}]
 122 set  CM_RTC_RTC_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8520}]
 123 set  CM_PER_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8800}]
 124 set  CM_PER_L3_CLKCTRL               [expr       {$PRCM_BASE_ADDR     +  0x8820}]
 125 set  CM_PER_AES0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8828}]
 126 set  CM_PER_DES_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8830}]
 127 set  CM_PER_CRYPTODMA_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8838}]
 128 set  CM_PER_L3_INSTR_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8840}]
 129 set  CM_PER_MSTR_EXPS_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8848}]
 130 set  CM_PER_OCMCRAM_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8850}]
 131 set  CM_PER_SHA0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8858}]
 132 set  CM_PER_SLV_EXPS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8860}]
 133 set  CM_PER_VPFE0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8868}]
 134 set  CM_PER_VPFE1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8870}]
 135 set  CM_PER_TPCC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8878}]
 136 set  CM_PER_TPTC0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8880}]
 137 set  CM_PER_TPTC1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8888}]
 138 set  CM_PER_TPTC2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8890}]
 139 set  CM_PER_DLL_AGING_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8898}]
 140 set  CM_PER_L4HS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a0}]
 141 set  CM_PER_L4FW_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a8}]
 142 set  CM_PER_L3S_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8a00}]
 143 set  CM_PER_GPMC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a20}]
 144 set  CM_PER_IEEE5000_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8a28}]
 145 set  CM_PER_MCASP0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a38}]
 146 set  CM_PER_MCASP1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a40}]
 147 set  CM_PER_MMC2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a48}]
 148 set  CM_PER_QSPI_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a58}]
 149 set  CM_PER_USB_OTG_SS0_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a60}]
 150 set  CM_PER_USB_OTG_SS1_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a68}]
 151 set  CM_PER_ICSS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8b00}]
 152 set  CM_PER_ICSS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8b20}]
 153 set  CM_PER_L4LS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8c00}]
 154 set  CM_PER_L4LS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8c20}]
 155 set  CM_PER_DCAN0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c28}]
 156 set  CM_PER_DCAN1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c30}]
 157 set  CM_PER_EPWMSS0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c38}]
 158 set  CM_PER_EPWMSS1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c40}]
 159 set  CM_PER_EPWMSS2_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c48}]
 160 set  CM_PER_EPWMSS3_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c50}]
 161 set  CM_PER_EPWMSS4_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c58}]
 162 set  CM_PER_EPWMSS5_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c60}]
 163 set  CM_PER_ELM_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8c68}]
 164 set  CM_PER_GPIO1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c78}]
 165 set  CM_PER_GPIO2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c80}]
 166 set  CM_PER_GPIO3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c88}]
 167 set  CM_PER_GPIO4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c90}]
 168 set  CM_PER_GPIO5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c98}]
 169 set  CM_PER_HDQ1W_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8ca0}]
 170 set  CM_PER_I2C1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8ca8}]
 171 set  CM_PER_I2C2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cb0}]
 172 set  CM_PER_MAILBOX0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8cb8}]
 173 set  CM_PER_MMC0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc0}]
 174 set  CM_PER_MMC1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc8}]
 175 set  CM_PER_PKA_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8cd0}]
 176 set  CM_PER_RNG_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8ce0}]
 177 set  CM_PER_SPARE0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8ce8}]
 178 set  CM_PER_SPARE1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8cf0}]
 179 set  CM_PER_SPI0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d00}]
 180 set  CM_PER_SPI1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d08}]
 181 set  CM_PER_SPI2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d10}]
 182 set  CM_PER_SPI3_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d18}]
 183 set  CM_PER_SPI4_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d20}]
 184 set  CM_PER_SPINLOCK_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8d28}]
 185 set  CM_PER_TIMER2_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d30}]
 186 set  CM_PER_TIMER3_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d38}]
 187 set  CM_PER_TIMER4_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d40}]
 188 set  CM_PER_TIMER5_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d48}]
 189 set  CM_PER_TIMER6_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d50}]
 190 set  CM_PER_TIMER7_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d58}]
 191 set  CM_PER_TIMER8_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d60}]
 192 set  CM_PER_TIMER9_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d68}]
 193 set  CM_PER_TIMER10_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d70}]
 194 set  CM_PER_TIMER11_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d78}]
 195 set  CM_PER_UART1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d80}]
 196 set  CM_PER_UART2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d88}]
 197 set  CM_PER_UART3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d90}]
 198 set  CM_PER_UART4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d98}]
 199 set  CM_PER_UART5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8da0}]
 200 set  CM_PER_USBPHYOCP2SCP0_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8db8}]
 201 set  CM_PER_USBPHYOCP2SCP1_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8dc0}]
 202 set  CM_PER_EMIF_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8f00}]
 203 set  CM_PER_EMIF_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8f20}]
 204 set  CM_PER_DLL_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8f28}]
 205 set  CM_PER_EMIF_FW_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8f30}]
 206 set  CM_PER_OTFA_EMIF_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8f38}]
 207 set  CM_PER_DSS_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9200}]
 208 set  CM_PER_DSS_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x9220}]
 209 set  CM_PER_CPSW_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x9300}]
 210 set  CM_PER_CPGMAC0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x9320}]
 211 set  CM_PER_OCPWP_L3_CLKSTCTRL       [expr       {$PRCM_BASE_ADDR     +  0x9400}]
 212 set  CM_PER_OCPWP_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9420}]
 213
 214 set  CONTROL_BASE_ADDR               0x44e10000
 215 set  CONTROL_STATUS                  [expr       {$CONTROL_BASE_ADDR  +  0x0040}]
 216 set  DEVICE_ID                       [expr       {$CONTROL_BASE_ADDR  +  0x0600}]
 217 set  DEV_FEATURE                     [expr       {$CONTROL_BASE_ADDR  +  0x0604}]
 218 set  DEV_ATTRIBUTE                   [expr       {$CONTROL_BASE_ADDR  +  0x0610}]
 219 set  MAC_ID0_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0630}]
 220 set  MAC_ID0_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x0634}]
 221 set  MAC_ID1_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0638}]
 222 set  MAC_ID1_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x063c}]
 223 set  USB_VID_PID                     [expr       {$CONTROL_BASE_ADDR  +  0x07f4}]
 224 set  CONTROL_CONF_ECAP0_IN_PWM0_OUT  [expr       {$CONTROL_BASE_ADDR  +  0x0964}]
 225 set  CONTROL_CONF_SPI4_CS0           [expr       {$CONTROL_BASE_ADDR  +  0x0a5c}]
 226 set  CONTROL_CONF_SPI2_SCLK          [expr       {$CONTROL_BASE_ADDR  +  0x0a60}]
 227 set  CONTROL_CONF_SPI2_D0            [expr       {$CONTROL_BASE_ADDR  +  0x0a64}]
 228 set  CONTROL_CONF_XDMA_EVENT_INTR0   [expr       {$CONTROL_BASE_ADDR  +  0x0a70}]
 229 set  CONTROL_CONF_XDMA_EVENT_INTR1   [expr       {$CONTROL_BASE_ADDR  +  0x0a74}]
 230 set  CONTROL_CONF_GPMC_A0            [expr       {$CONTROL_BASE_ADDR  +  0x0840}]
 231 set  DDR_IO_CTRL                     [expr       {$CONTROL_BASE_ADDR  +  0x0e04}]
 232 set  VTP_CTRL_REG                    [expr       {$CONTROL_BASE_ADDR  +  0x0e0c}]
 233 set  VREF_CTRL                       [expr       {$CONTROL_BASE_ADDR  +  0x0e14}]
 234 set  DDR_CKE_CTRL                    [expr       {$CONTROL_BASE_ADDR  +  0x131c}]
 235 set  DDR_ADDRCTRL_IOCTRL             [expr       {$CONTROL_BASE_ADDR  +  0x1404}]
 236 set  DDR_ADDRCTRL_WD0_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x1408}]
 237 set  DDR_ADDRCTRL_WD1_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x140c}]
 238 set  DDR_DATA0_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1440}]
 239 set  DDR_DATA1_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1444}]
 240 set  DDR_DATA2_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1448}]
 241 set  DDR_DATA3_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x144c}]
 242 set  EMIF_SDRAM_CONFIG_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1460}]
 243 set  EMIF_SDRAM_STATUS_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1464}]
 244
 245 set  GPIO0_BASE_ADDR                 0x44e07000
 246 set  GPIO0_SYSCONFIG                 [expr       {$GPIO0_BASE_ADDR    +  0x0010}]
 247 set  GPIO0_SYSSTATUS                 [expr       {$GPIO0_BASE_ADDR    +  0x0114}]
 248 set  GPIO0_CTRL                      [expr       {$GPIO0_BASE_ADDR    +  0x0130}]
 249 set  GPIO0_OE                        [expr       {$GPIO0_BASE_ADDR    +  0x0134}]
 250 set  GPIO0_CLEARDATAOUT              [expr       {$GPIO0_BASE_ADDR    +  0x0190}]
 251 set  GPIO0_SETDATAOUT                [expr       {$GPIO0_BASE_ADDR    +  0x0194}]
 252
 253 set  GPIO5_BASE_ADDR                 0x48322000
 254 set  GPIO5_SYSCONFIG                 [expr       {$GPIO5_BASE_ADDR    +  0x0010}]
 255 set  GPIO5_SYSSTATUS                 [expr       {$GPIO5_BASE_ADDR    +  0x0114}]
 256 set  GPIO5_CTRL                      [expr       {$GPIO5_BASE_ADDR    +  0x0130}]
 257 set  GPIO5_OE                        [expr       {$GPIO5_BASE_ADDR    +  0x0134}]
 258 set  GPIO5_CLEARDATAOUT              [expr       {$GPIO5_BASE_ADDR    +  0x0190}]
 259 set  GPIO5_SETDATAOUT                [expr       {$GPIO5_BASE_ADDR    +  0x0194}]
 260
 261 set  GPIO1_BASE_ADDR                 0x4804c000
 262 set  GPIO1_SYSCONFIG                 [expr       {$GPIO1_BASE_ADDR    +  0x0010}]
 263 set  GPIO1_SYSSTATUS                 [expr       {$GPIO1_BASE_ADDR    +  0x0114}]
 264 set  GPIO1_CTRL                      [expr       {$GPIO1_BASE_ADDR    +  0x0130}]
 265 set  GPIO1_OE                        [expr       {$GPIO1_BASE_ADDR    +  0x0134}]
 266 set  GPIO1_CLEARDATAOUT              [expr       {$GPIO1_BASE_ADDR    +  0x0190}]
 267 set  GPIO1_SETDATAOUT                [expr       {$GPIO1_BASE_ADDR    +  0x0194}]
 268
 269 set  EMIF_BASE_ADDR                  0x4c000000
 270 set  EMIF_STATUS                     [expr       {$EMIF_BASE_ADDR     +  0x0004}]
 271 set  EMIF_SDRAM_CONFIG               [expr       {$EMIF_BASE_ADDR     +  0x0008}]
 272 set  EMIF_SDRAM_CONFIG_2             [expr       {$EMIF_BASE_ADDR     +  0x000c}]
 273 set  EMIF_SDRAM_REF_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0010}]
 274 set  EMIF_SDRAM_REF_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0014}]
 275 set  EMIF_SDRAM_TIM_1                [expr       {$EMIF_BASE_ADDR     +  0x0018}]
 276 set  EMIF_SDRAM_TIM_1_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x001c}]
 277 set  EMIF_SDRAM_TIM_2                [expr       {$EMIF_BASE_ADDR     +  0x0020}]
 278 set  EMIF_SDRAM_TIM_2_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x0024}]
 279 set  EMIF_SDRAM_TIM_3                [expr       {$EMIF_BASE_ADDR     +  0x0028}]
 280 set  EMIF_SDRAM_TIM_3_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x002c}]
 281 set  EMIF_LPDDR2_NVM_TIM             [expr       {$EMIF_BASE_ADDR     +  0x0030}]
 282 set  EMIF_LPDDR2_NVM_TIM_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0034}]
 283 set  EMIF_PWR_MGMT_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x0038}]
 284 set  EMIF_PWR_MGMT_CTRL_SHDW         [expr       {$EMIF_BASE_ADDR     +  0x003c}]
 285 set  EMIF_LPDDR2_MODE_REG_DATA       [expr       {$EMIF_BASE_ADDR     +  0x0040}]
 286 set  EMIF_LPDDR2_MODE_REG_CFG        [expr       {$EMIF_BASE_ADDR     +  0x0050}]
 287 set  EMIF_OCP_CONFIG                 [expr       {$EMIF_BASE_ADDR     +  0x0054}]
 288 set  EMIF_OCP_CFG_VAL_1              [expr       {$EMIF_BASE_ADDR     +  0x0058}]
 289 set  EMIF_OCP_CFG_VAL_2              [expr       {$EMIF_BASE_ADDR     +  0x005c}]
 290 set  EMIF_IODFT_TLGC                 [expr       {$EMIF_BASE_ADDR     +  0x0060}]
 291 set  EMIF_IODFT_CTRL_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0064}]
 292 set  EMIF_IODFT_ADDR_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0068}]
 293 set  EMIF_IODFT_DATA_MISR_RSLT_1     [expr       {$EMIF_BASE_ADDR     +  0x006c}]
 294 set  EMIF_IODFT_DATA_MISR_RSLT_2     [expr       {$EMIF_BASE_ADDR     +  0x0070}]
 295 set  EMIF_IODFT_DATA_MISR_RSLT_3     [expr       {$EMIF_BASE_ADDR     +  0x0074}]
 296 set  EMIF_PERF_CNT_1                 [expr       {$EMIF_BASE_ADDR     +  0x0080}]
 297 set  EMIF_PERF_CNT_2                 [expr       {$EMIF_BASE_ADDR     +  0x0084}]
 298 set  EMIF_PERF_CNT_CFG               [expr       {$EMIF_BASE_ADDR     +  0x0088}]
 299 set  EMIF_PERF_CNT_SEL               [expr       {$EMIF_BASE_ADDR     +  0x008c}]
 300 set  EMIF_PERF_CNT_TIM               [expr       {$EMIF_BASE_ADDR     +  0x0090}]
 301 set  EMIF_MISC_REG                   [expr       {$EMIF_BASE_ADDR     +  0x0094}]
 302 set  EMIF_DLL_CALIB_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0098}]
 303 set  EMIF_DLL_CALIB_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x009c}]
 304 set  EMIF_IRQ_EOI                    [expr       {$EMIF_BASE_ADDR     +  0x00a0}]
 305 set  EMIF_IRQSTATUS_RAW_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00a4}]
 306 set  EMIF_IRQSTATUS_SYS              [expr       {$EMIF_BASE_ADDR     +  0x00ac}]
 307 set  EMIF_IRQENABLE_SET_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00b4}]
 308 set  EMIF_IRQENABLE_CLR_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00bc}]
 309 set  EMIF_ZQ_CONFIG                  [expr       {$EMIF_BASE_ADDR     +  0x00c8}]
 310 set  EMIF_TEMP_ALERT_CONFIG          [expr       {$EMIF_BASE_ADDR     +  0x00cc}]
 311 set  EMIF_OCP_ERR_LOG                [expr       {$EMIF_BASE_ADDR     +  0x00d0}]
 312 set  EMIF_RDWR_LVL_RMP_WIN           [expr       {$EMIF_BASE_ADDR     +  0x00d4}]
 313 set  EMIF_RDWR_LVL_RMP_CTRL          [expr       {$EMIF_BASE_ADDR     +  0x00d8}]
 314 set  EMIF_RDWR_LVL_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x00dc}]
 315 set  EMIF_DDR_PHY_CTRL_1             [expr       {$EMIF_BASE_ADDR     +  0x00e4}]
 316 set  EMIF_DDR_PHY_CTRL_1_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x00e8}]
 317 set  EMIF_DDR_PHY_CTRL_2             [expr       {$EMIF_BASE_ADDR     +  0x00ec}]
 318 set  EMIF_PRI_COS_MAP                [expr       {$EMIF_BASE_ADDR     +  0x0100}]
 319 set  EMIF_CONNID_COS_1_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0104}]
 320 set  EMIF_CONNID_COS_2_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0108}]
 321 set  ECC_CTRL                        [expr       {$EMIF_BASE_ADDR     +  0x0110}]
 322 set  ECC_ADDR_RNG_1                  [expr       {$EMIF_BASE_ADDR     +  0x0114}]
 323 set  ECC_ADDR_RNG_2                  [expr       {$EMIF_BASE_ADDR     +  0x0118}]
 324 set  EMIF_RD_WR_EXEC_THRSH           [expr       {$EMIF_BASE_ADDR     +  0x0120}]
 325 set  COS_CONFIG                      [expr       {$EMIF_BASE_ADDR     +  0x0124}]
 326
 327 set  PHY_STATUS_1                    [expr       {$EMIF_BASE_ADDR     +  0x0144}]
 328 set  PHY_STATUS_2                    [expr       {$EMIF_BASE_ADDR     +  0x0148}]
 329 set  PHY_STATUS_3                    [expr       {$EMIF_BASE_ADDR     +  0x014c}]
 330 set  PHY_STATUS_4                    [expr       {$EMIF_BASE_ADDR     +  0x0150}]
 331 set  PHY_STATUS_5                    [expr       {$EMIF_BASE_ADDR     +  0x0154}]
 332 set  PHY_STATUS_6                    [expr       {$EMIF_BASE_ADDR     +  0x0158}]
 333 set  PHY_STATUS_7                    [expr       {$EMIF_BASE_ADDR     +  0x015c}]
 334 set  PHY_STATUS_8                    [expr       {$EMIF_BASE_ADDR     +  0x0160}]
 335 set  PHY_STATUS_9                    [expr       {$EMIF_BASE_ADDR     +  0x0164}]
 336 set  PHY_STATUS_10                   [expr       {$EMIF_BASE_ADDR     +  0x0168}]
 337 set  PHY_STATUS_11                   [expr       {$EMIF_BASE_ADDR     +  0x016c}]
 338 set  PHY_STATUS_12                   [expr       {$EMIF_BASE_ADDR     +  0x0170}]
 339 set  PHY_STATUS_13                   [expr       {$EMIF_BASE_ADDR     +  0x0174}]
 340 set  PHY_STATUS_14                   [expr       {$EMIF_BASE_ADDR     +  0x0178}]
 341 set  PHY_STATUS_15                   [expr       {$EMIF_BASE_ADDR     +  0x017c}]
 342 set  PHY_STATUS_16                   [expr       {$EMIF_BASE_ADDR     +  0x0180}]
 343 set  PHY_STATUS_17                   [expr       {$EMIF_BASE_ADDR     +  0x0184}]
 344 set  PHY_STATUS_18                   [expr       {$EMIF_BASE_ADDR     +  0x0188}]
 345 set  PHY_STATUS_19                   [expr       {$EMIF_BASE_ADDR     +  0x018c}]
 346 set  PHY_STATUS_20                   [expr       {$EMIF_BASE_ADDR     +  0x0190}]
 347 set  PHY_STATUS_21                   [expr       {$EMIF_BASE_ADDR     +  0x0194}]
 348 set  PHY_STATUS_22                   [expr       {$EMIF_BASE_ADDR     +  0x0198}]
 349 set  PHY_STATUS_23                   [expr       {$EMIF_BASE_ADDR     +  0x019c}]
 350 set  PHY_STATUS_24                   [expr       {$EMIF_BASE_ADDR     +  0x01a0}]
 351 set  PHY_STATUS_25                   [expr       {$EMIF_BASE_ADDR     +  0x01a4}]
 352 set  PHY_STATUS_26                   [expr       {$EMIF_BASE_ADDR     +  0x01a8}]
 353 set  PHY_STATUS_27                   [expr       {$EMIF_BASE_ADDR     +  0x01ac}]
 354 set  PHY_STATUS_28                   [expr       {$EMIF_BASE_ADDR     +  0x01b0}]
 355
 356 set  EXT_PHY_CTRL_1                  [expr       {$EMIF_BASE_ADDR     +  0x0200}]
 357 set  EXT_PHY_CTRL_1_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0204}]
 358 set  EXT_PHY_CTRL_2                  [expr       {$EMIF_BASE_ADDR     +  0x0208}]
 359 set  EXT_PHY_CTRL_2_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x020c}]
 360 set  EXT_PHY_CTRL_3                  [expr       {$EMIF_BASE_ADDR     +  0x0210}]
 361 set  EXT_PHY_CTRL_3_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0214}]
 362 set  EXT_PHY_CTRL_4                  [expr       {$EMIF_BASE_ADDR     +  0x0218}]
 363 set  EXT_PHY_CTRL_4_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x021c}]
 364 set  EXT_PHY_CTRL_5                  [expr       {$EMIF_BASE_ADDR     +  0x0220}]
 365 set  EXT_PHY_CTRL_5_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0224}]
 366 set  EXT_PHY_CTRL_6                  [expr       {$EMIF_BASE_ADDR     +  0x0228}]
 367 set  EXT_PHY_CTRL_6_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x022c}]
 368 set  EXT_PHY_CTRL_7                  [expr       {$EMIF_BASE_ADDR     +  0x0230}]
 369 set  EXT_PHY_CTRL_7_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0234}]
 370 set  EXT_PHY_CTRL_8                  [expr       {$EMIF_BASE_ADDR     +  0x0238}]
 371 set  EXT_PHY_CTRL_8_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x023c}]
 372 set  EXT_PHY_CTRL_9                  [expr       {$EMIF_BASE_ADDR     +  0x0240}]
 373 set  EXT_PHY_CTRL_9_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0244}]
 374 set  EXT_PHY_CTRL_10                 [expr       {$EMIF_BASE_ADDR     +  0x0248}]
 375 set  EXT_PHY_CTRL_10_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x024c}]
 376 set  EXT_PHY_CTRL_11                 [expr       {$EMIF_BASE_ADDR     +  0x0250}]
 377 set  EXT_PHY_CTRL_11_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0254}]
 378 set  EXT_PHY_CTRL_12                 [expr       {$EMIF_BASE_ADDR     +  0x0258}]
 379 set  EXT_PHY_CTRL_12_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x025c}]
 380 set  EXT_PHY_CTRL_13                 [expr       {$EMIF_BASE_ADDR     +  0x0260}]
 381 set  EXT_PHY_CTRL_13_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0264}]
 382 set  EXT_PHY_CTRL_14                 [expr       {$EMIF_BASE_ADDR     +  0x0268}]
 383 set  EXT_PHY_CTRL_14_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x026c}]
 384 set  EXT_PHY_CTRL_15                 [expr       {$EMIF_BASE_ADDR     +  0x0270}]
 385 set  EXT_PHY_CTRL_15_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0274}]
 386 set  EXT_PHY_CTRL_16                 [expr       {$EMIF_BASE_ADDR     +  0x0278}]
 387 set  EXT_PHY_CTRL_16_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x027c}]
 388 set  EXT_PHY_CTRL_17                 [expr       {$EMIF_BASE_ADDR     +  0x0280}]
 389 set  EXT_PHY_CTRL_17_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0284}]
 390 set  EXT_PHY_CTRL_18                 [expr       {$EMIF_BASE_ADDR     +  0x0288}]
 391 set  EXT_PHY_CTRL_18_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x028c}]
 392 set  EXT_PHY_CTRL_19                 [expr       {$EMIF_BASE_ADDR     +  0x0290}]
 393 set  EXT_PHY_CTRL_19_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0294}]
 394 set  EXT_PHY_CTRL_20                 [expr       {$EMIF_BASE_ADDR     +  0x0298}]
 395 set  EXT_PHY_CTRL_20_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x029c}]
 396 set  EXT_PHY_CTRL_21                 [expr       {$EMIF_BASE_ADDR     +  0x02a0}]
 397 set  EXT_PHY_CTRL_21_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02a4}]
 398 set  EXT_PHY_CTRL_22                 [expr       {$EMIF_BASE_ADDR     +  0x02a8}]
 399 set  EXT_PHY_CTRL_22_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ac}]
 400 set  EXT_PHY_CTRL_23                 [expr       {$EMIF_BASE_ADDR     +  0x02b0}]
 401 set  EXT_PHY_CTRL_23_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02b4}]
 402 set  EXT_PHY_CTRL_24                 [expr       {$EMIF_BASE_ADDR     +  0x02b8}]
 403 set  EXT_PHY_CTRL_24_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02bc}]
 404 set  EXT_PHY_CTRL_25                 [expr       {$EMIF_BASE_ADDR     +  0x02c0}]
 405 set  EXT_PHY_CTRL_25_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02c4}]
 406 set  EXT_PHY_CTRL_26                 [expr       {$EMIF_BASE_ADDR     +  0x02c8}]
 407 set  EXT_PHY_CTRL_26_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02cc}]
 408 set  EXT_PHY_CTRL_27                 [expr       {$EMIF_BASE_ADDR     +  0x02d0}]
 409 set  EXT_PHY_CTRL_27_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02d4}]
 410 set  EXT_PHY_CTRL_28                 [expr       {$EMIF_BASE_ADDR     +  0x02d8}]
 411 set  EXT_PHY_CTRL_28_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02dc}]
 412 set  EXT_PHY_CTRL_29                 [expr       {$EMIF_BASE_ADDR     +  0x02e0}]
 413 set  EXT_PHY_CTRL_29_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02e4}]
 414 set  EXT_PHY_CTRL_30                 [expr       {$EMIF_BASE_ADDR     +  0x02e8}]
 415 set  EXT_PHY_CTRL_30_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ec}]
 416 set  EXT_PHY_CTRL_31                 [expr       {$EMIF_BASE_ADDR     +  0x02f0}]
 417 set  EXT_PHY_CTRL_31_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02f4}]
 418 set  EXT_PHY_CTRL_32                 [expr       {$EMIF_BASE_ADDR     +  0x02f8}]
 419 set  EXT_PHY_CTRL_32_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02fc}]
 420 set  EXT_PHY_CTRL_33                 [expr       {$EMIF_BASE_ADDR     +  0x0300}]
 421 set  EXT_PHY_CTRL_33_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0304}]
 422 set  EXT_PHY_CTRL_34                 [expr       {$EMIF_BASE_ADDR     +  0x0308}]
 423 set  EXT_PHY_CTRL_34_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x030c}]
 424 set  EXT_PHY_CTRL_35                 [expr       {$EMIF_BASE_ADDR     +  0x0310}]
 425 set  EXT_PHY_CTRL_35_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0314}]
 426 set  EXT_PHY_CTRL_36                 [expr       {$EMIF_BASE_ADDR     +  0x0318}]
 427 set  EXT_PHY_CTRL_36_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x031c}]
 428
 429 set  WDT1_BASE_ADDR                  0x44e35000
 430 set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
 431 set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
 432
 433 set  RTC_BASE_ADDR                   0x44e3e000
 434 set  RTC_KICK0R                      [expr       {$RTC_BASE_ADDR      +  0x6c}]
 435 set  RTC_KICK1R                      [expr       {$RTC_BASE_ADDR      +  0x70}]
 436
 437
 438 if { [info exists CHIPNAME] } {
 439    set _CHIPNAME $CHIPNAME
 440 } else {
 441    set _CHIPNAME am437x
 442 }
 443
 444 set JRC_MODULE          icepick_d
 445 set DEBUGSS_MODULE      debugss
 446 set M3_MODULE           m3_wakeupss
 447
 448 set JRC_NAME            $_CHIPNAME.$JRC_MODULE
 449 set DEBUGSS_NAME        $_CHIPNAME.$DEBUGSS_MODULE
 450 set M3_NAME             $_CHIPNAME.$M3_MODULE
 451 set _TARGETNAME         $_CHIPNAME.mpuss
 452
 453 #
 454 # M3 WakeupSS DAP
 455 #
 456 if { [info exists M3_DAP_TAPID] } {
 457         set _M3_DAP_TAPID $M3_DAP_TAPID
 458 } else {
 459         set _M3_DAP_TAPID 0x4b6b902f
 460 }
 461 jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
 462 jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
 463 dap create $M3_NAME.dap -chain-position $M3_NAME
 464
 465 #
 466 # DebugSS DAP
 467 #
 468 if { [info exists DAP_TAPID] } {
 469    set _DAP_TAPID $DAP_TAPID
 470 } else {
 471    set _DAP_TAPID 0x46b6902f
 472 }
 473 jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
 474 jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
 475 dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
 476
 477 #
 478 # ICEpick-D (JTAG route controller)
 479 #
 480 if { [info exists JRC_TAPID] } {
 481    set _JRC_TAPID $JRC_TAPID
 482 } else {
 483    set _JRC_TAPID 0x0b98c02f
 484 }
 485 jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
 486 jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
 487  # some TCK tycles are required to activate the DEBUG power domain
 488 jtag configure $JRC_NAME -event post-reset "runtest 100"
 489
 490 #
 491 # Cortex-A9 target
 492 #
 493 target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
 494
 495
 496 # SRAM: 256K at 0x4030.0000
 497 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
 498
 499 # Disables watchdog timer after reset otherwise board won't stay in
 500 # halted state.
 501 proc disable_watchdog { } {
 502         global WDT1_WSPR
 503         global WDT1_W_PEND_WSPR
 504         global _TARGETNAME
 505
 506         set curstate [$_TARGETNAME curstate]
 507
 508         if { [string compare $curstate halted] == 0 } {
 509                 set WDT_DISABLE_SEQ1    0xaaaa
 510                 set WDT_DISABLE_SEQ2    0x5555
 511
 512                 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
 513
 514                 # Empty body to make sure this executes as fast as possible.
 515                 # We don't want any delays here otherwise romcode might start
 516                 # executing and end up changing state of certain IPs.
 517                 while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
 518
 519                 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
 520                 while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
 521         }
 522 }
 523
 524 proc ceil { x y } {
 525         return [ expr {($x + $y - 1) / $y} ]
 526 }
 527
 528 proc device_type { } {
 529         global CONTROL_STATUS
 530
 531         set tmp [ mrw $CONTROL_STATUS ]
 532         set tmp [ expr {$tmp & 0x700} ]
 533         set tmp [ expr {$tmp >> 8} ]
 534
 535         return $tmp
 536 }
 537
 538 proc get_input_clock_frequency { } {
 539         global CONTROL_STATUS
 540
 541         if { [ device_type ] != 3 } {
 542                 error "Unknown device type\n"
 543                 return -1
 544         }
 545
 546         set freq [ mrw $CONTROL_STATUS ]
 547         set freq [ expr {$freq & 0x00c00000} ]
 548         set freq [ expr {$freq >> 22} ]
 549
 550         switch $freq {
 551                 0 {
 552                         set CLKIN 19200000
 553                 }
 554
 555                 1 {
 556                         set CLKIN 24000000
 557                 }
 558
 559                 2 {
 560                         set CLKIN 25000000
 561                 }
 562
 563                 3 {
 564                         set CLKIN 26000000
 565                 }
 566         }
 567
 568         return $CLKIN
 569 }
 570
 571 proc mpu_pll_config { CLKIN N M M2 } {
 572         global CM_CLKMODE_DPLL_MPU
 573         global CM_CLKSEL_DPLL_MPU
 574         global CM_DIV_M2_DPLL_MPU
 575         global CM_IDLEST_DPLL_MPU
 576
 577         set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
 578         set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
 579
 580         mww $CM_CLKMODE_DPLL_MPU 0x4
 581         while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
 582
 583         set clksel [ expr {$clksel & (~0x7ffff)} ]
 584         set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
 585         mww $CM_CLKSEL_DPLL_MPU $clksel
 586
 587         set div_m2 [ expr {$div_m2 & (~0x1f)} ]
 588         set div_m2 [ expr {$div_m2 | $M2} ]
 589         mww $CM_DIV_M2_DPLL_MPU $div_m2
 590
 591         mww $CM_CLKMODE_DPLL_MPU 0x7
 592         while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
 593
 594         echo "MPU DPLL locked"
 595 }
 596
 597 proc core_pll_config { CLKIN N M M4 M5 M6 } {
 598         global CM_CLKMODE_DPLL_CORE
 599         global CM_CLKSEL_DPLL_CORE
 600         global CM_DIV_M4_DPLL_CORE
 601         global CM_DIV_M5_DPLL_CORE
 602         global CM_DIV_M6_DPLL_CORE
 603         global CM_IDLEST_DPLL_CORE
 604
 605         set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
 606
 607         mww $CM_CLKMODE_DPLL_CORE 0x4
 608         while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
 609
 610         set clksel [ expr {$clksel & (~0x7ffff)} ]
 611         set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
 612         mww $CM_CLKSEL_DPLL_CORE $clksel
 613         mww $CM_DIV_M4_DPLL_CORE $M4
 614         mww $CM_DIV_M5_DPLL_CORE $M5
 615         mww $CM_DIV_M6_DPLL_CORE $M6
 616
 617         mww $CM_CLKMODE_DPLL_CORE 0x7
 618         while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
 619
 620         echo "CORE DPLL locked"
 621 }
 622
 623 proc per_pll_config { CLKIN N M M2 } {
 624         global CM_CLKMODE_DPLL_PER
 625         global CM_CLKSEL_DPLL_PER
 626         global CM_DIV_M2_DPLL_PER
 627         global CM_IDLEST_DPLL_PER
 628
 629         set x [ expr {$M * $CLKIN / 1000000} ]
 630         set y [ expr {($N + 1) * 250} ]
 631         set sd [ ceil $x $y ]
 632
 633         set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
 634         set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
 635
 636         mww $CM_CLKMODE_DPLL_PER 0x4
 637         while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
 638
 639         set clksel [ expr {$clksel & (~0xff0fffff)} ]
 640         set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
 641         set clksel [ expr {$clksel | ($sd << 24)} ]
 642         mww $CM_CLKSEL_DPLL_PER $clksel
 643
 644         set div_m2 [ expr {0xffffff80 | $M2} ]
 645
 646         mww $CM_CLKMODE_DPLL_PER 0x7
 647         while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
 648
 649         echo "PER DPLL locked"
 650 }
 651
 652 proc ddr_pll_config { CLKIN N M M2 M4 } {
 653         global CM_CLKMODE_DPLL_DDR
 654         global CM_CLKSEL_DPLL_DDR
 655         global CM_DIV_M2_DPLL_DDR
 656         global CM_DIV_M4_DPLL_DDR
 657         global CM_IDLEST_DPLL_DDR
 658
 659         set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
 660         set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
 661
 662         mww $CM_CLKMODE_DPLL_DDR 0x4
 663         while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
 664
 665         set clksel [ expr {$clksel & (~0x7ffff)} ]
 666         set clksel [ expr {$clksel | ($M << 8) | $N} ]
 667         mww $CM_CLKSEL_DPLL_DDR $clksel
 668
 669         set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]
 670         mww $CM_DIV_M2_DPLL_DDR $div_m2
 671         mww $CM_DIV_M4_DPLL_DDR $M4
 672
 673         mww $CM_CLKMODE_DPLL_DDR 0x7
 674         while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
 675
 676         echo "DDR DPLL Locked"
 677 }
 678
 679 proc config_opp100 { } {
 680         set CLKIN [ get_input_clock_frequency ]
 681
 682         if { $CLKIN == -1 } {
 683                 return -1
 684         }
 685
 686         switch $CLKIN {
 687                 24000000 {
 688                         mpu_pll_config   $CLKIN  0  25   1
 689                         core_pll_config  $CLKIN  2  125  10  8  4
 690                         per_pll_config   $CLKIN  9  400  5
 691                         ddr_pll_config   $CLKIN  2  50   1   2
 692                 }
 693
 694                 25000000 {
 695                         mpu_pll_config   $CLKIN  0  24   1
 696                         core_pll_config  $CLKIN  0  40   10  8  4
 697                         per_pll_config   $CLKIN  9  384  5
 698                         ddr_pll_config   $CLKIN  0  16   1   2
 699                 }
 700
 701                 26000000 {
 702                         mpu_pll_config   $CLKIN  12  300  1
 703                         core_pll_config  $CLKIN  12  500  10  8  4
 704                         per_pll_config   $CLKIN  12  480  5
 705                         ddr_pll_config   $CLKIN  12  200  1   2
 706                 }
 707
 708                 19200000 {
 709                         mpu_pll_config   $CLKIN  3   125  1
 710                         core_pll_config  $CLKIN  11  625  10  8  4
 711                         per_pll_config   $CLKIN  7   400  5
 712                         ddr_pll_config   $CLKIN  2   125  1   2
 713                 }
 714         }
 715 }
 716
 717 proc emif_prcm_clk_enable { } {
 718         global CM_PER_EMIF_FW_CLKCTRL
 719         global CM_PER_EMIF_CLKCTRL
 720
 721         mww $CM_PER_EMIF_FW_CLKCTRL 0x02
 722         mww $CM_PER_EMIF_CLKCTRL 0x02
 723
 724         while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
 725 }
 726
 727 proc vtp_enable { } {
 728         global VTP_CTRL_REG
 729
 730         set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
 731         mww $VTP_CTRL_REG $vtp
 732
 733         set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
 734         mww $VTP_CTRL_REG $vtp
 735
 736         set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
 737         mww $VTP_CTRL_REG $vtp
 738
 739 }
 740
 741 proc config_ddr_ioctrl { } {
 742         global DDR_ADDRCTRL_IOCTRL
 743         global DDR_ADDRCTRL_WD0_IOCTRL
 744         global DDR_ADDRCTRL_WD1_IOCTRL
 745         global DDR_CKE_CTRL
 746         global DDR_DATA0_IOCTRL
 747         global DDR_DATA1_IOCTRL
 748         global DDR_DATA2_IOCTRL
 749         global DDR_DATA3_IOCTRL
 750         global DDR_IO_CTRL
 751
 752         mww $DDR_ADDRCTRL_IOCTRL        0x84
 753         mww $DDR_ADDRCTRL_WD0_IOCTRL    0x00
 754         mww $DDR_ADDRCTRL_WD1_IOCTRL    0x00
 755         mww $DDR_DATA0_IOCTRL           0x84
 756         mww $DDR_DATA1_IOCTRL           0x84
 757         mww $DDR_DATA2_IOCTRL           0x84
 758         mww $DDR_DATA3_IOCTRL           0x84
 759
 760         mww $DDR_IO_CTRL                0x00
 761         mww $DDR_CKE_CTRL               0x03
 762 }
 763
 764 proc config_ddr_phy { } {
 765         global EMIF_DDR_PHY_CTRL_1
 766         global EMIF_DDR_PHY_CTRL_1_SHDW
 767
 768         global EXT_PHY_CTRL_1
 769         global EXT_PHY_CTRL_1_SHDW
 770         global EXT_PHY_CTRL_2
 771         global EXT_PHY_CTRL_2_SHDW
 772         global EXT_PHY_CTRL_3
 773         global EXT_PHY_CTRL_3_SHDW
 774         global EXT_PHY_CTRL_4
 775         global EXT_PHY_CTRL_4_SHDW
 776         global EXT_PHY_CTRL_5
 777         global EXT_PHY_CTRL_5_SHDW
 778         global EXT_PHY_CTRL_6
 779         global EXT_PHY_CTRL_6_SHDW
 780         global EXT_PHY_CTRL_7
 781         global EXT_PHY_CTRL_7_SHDW
 782         global EXT_PHY_CTRL_8
 783         global EXT_PHY_CTRL_8_SHDW
 784         global EXT_PHY_CTRL_9
 785         global EXT_PHY_CTRL_9_SHDW
 786         global EXT_PHY_CTRL_10
 787         global EXT_PHY_CTRL_10_SHDW
 788         global EXT_PHY_CTRL_11
 789         global EXT_PHY_CTRL_11_SHDW
 790         global EXT_PHY_CTRL_12
 791         global EXT_PHY_CTRL_12_SHDW
 792         global EXT_PHY_CTRL_13
 793         global EXT_PHY_CTRL_13_SHDW
 794         global EXT_PHY_CTRL_14
 795         global EXT_PHY_CTRL_14_SHDW
 796         global EXT_PHY_CTRL_15
 797         global EXT_PHY_CTRL_15_SHDW
 798         global EXT_PHY_CTRL_16
 799         global EXT_PHY_CTRL_16_SHDW
 800         global EXT_PHY_CTRL_17
 801         global EXT_PHY_CTRL_17_SHDW
 802         global EXT_PHY_CTRL_18
 803         global EXT_PHY_CTRL_18_SHDW
 804         global EXT_PHY_CTRL_19
 805         global EXT_PHY_CTRL_19_SHDW
 806         global EXT_PHY_CTRL_20
 807         global EXT_PHY_CTRL_20_SHDW
 808         global EXT_PHY_CTRL_21
 809         global EXT_PHY_CTRL_21_SHDW
 810         global EXT_PHY_CTRL_22
 811         global EXT_PHY_CTRL_22_SHDW
 812         global EXT_PHY_CTRL_23
 813         global EXT_PHY_CTRL_23_SHDW
 814         global EXT_PHY_CTRL_24
 815         global EXT_PHY_CTRL_24_SHDW
 816         global EXT_PHY_CTRL_25
 817         global EXT_PHY_CTRL_25_SHDW
 818         global EXT_PHY_CTRL_26
 819         global EXT_PHY_CTRL_26_SHDW
 820         global EXT_PHY_CTRL_27
 821         global EXT_PHY_CTRL_27_SHDW
 822         global EXT_PHY_CTRL_28
 823         global EXT_PHY_CTRL_28_SHDW
 824         global EXT_PHY_CTRL_29
 825         global EXT_PHY_CTRL_29_SHDW
 826         global EXT_PHY_CTRL_30
 827         global EXT_PHY_CTRL_30_SHDW
 828         global EXT_PHY_CTRL_31
 829         global EXT_PHY_CTRL_31_SHDW
 830         global EXT_PHY_CTRL_32
 831         global EXT_PHY_CTRL_32_SHDW
 832         global EXT_PHY_CTRL_33
 833         global EXT_PHY_CTRL_33_SHDW
 834         global EXT_PHY_CTRL_34
 835         global EXT_PHY_CTRL_34_SHDW
 836         global EXT_PHY_CTRL_35
 837         global EXT_PHY_CTRL_35_SHDW
 838         global EXT_PHY_CTRL_36
 839         global EXT_PHY_CTRL_36_SHDW
 840
 841         mww $EMIF_DDR_PHY_CTRL_1        0x8009
 842         mww $EMIF_DDR_PHY_CTRL_1_SHDW   0x8009
 843
 844         set slave_ratio         0x80
 845         set gatelvl_init_ratio  0x20
 846         set wr_dqs_slave_delay  0x60
 847         set rd_dqs_slave_delay  0x60
 848         set dq_offset           0x40
 849         set gatelvl_init_mode   0x01
 850         set wr_data_slave_delay 0x80
 851         set gatelvl_num_dq0 0x0f
 852         set wrlvl_num_dq0 0x0f
 853
 854         mww $EXT_PHY_CTRL_1        [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
 855         mww $EXT_PHY_CTRL_1_SHDW   [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
 856         mww $EXT_PHY_CTRL_26       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 857         mww $EXT_PHY_CTRL_26_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 858         mww $EXT_PHY_CTRL_27       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 859         mww $EXT_PHY_CTRL_27_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 860         mww $EXT_PHY_CTRL_28       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 861         mww $EXT_PHY_CTRL_28_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 862         mww $EXT_PHY_CTRL_29       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 863         mww $EXT_PHY_CTRL_29_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 864         mww $EXT_PHY_CTRL_30       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 865         mww $EXT_PHY_CTRL_30_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
 866         mww $EXT_PHY_CTRL_31       0x00
 867         mww $EXT_PHY_CTRL_31_SHDW  0x00
 868         mww $EXT_PHY_CTRL_32       0x00
 869         mww $EXT_PHY_CTRL_32_SHDW  0x00
 870         mww $EXT_PHY_CTRL_33       0x00
 871         mww $EXT_PHY_CTRL_33_SHDW  0x00
 872         mww $EXT_PHY_CTRL_34       0x00
 873         mww $EXT_PHY_CTRL_34_SHDW  0x00
 874         mww $EXT_PHY_CTRL_35       0x00
 875         mww $EXT_PHY_CTRL_35_SHDW  0x00
 876         mww $EXT_PHY_CTRL_22       0x00
 877         mww $EXT_PHY_CTRL_22_SHDW  0x00
 878         mww $EXT_PHY_CTRL_23       [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
 879         mww $EXT_PHY_CTRL_23_SHDW  [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]
 880         mww $EXT_PHY_CTRL_24       [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]
 881         mww $EXT_PHY_CTRL_24_SHDW  [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]
 882         mww $EXT_PHY_CTRL_25       [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
 883         mww $EXT_PHY_CTRL_25_SHDW  [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
 884         mww $EXT_PHY_CTRL_36       [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
 885         mww $EXT_PHY_CTRL_36_SHDW  [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
 886 }
 887
 888 proc config_ddr_timing { } {
 889         global EMIF_SDRAM_TIM_1
 890         global EMIF_SDRAM_TIM_2
 891         global EMIF_SDRAM_TIM_3
 892         global EMIF_SDRAM_TIM_1_SHDW
 893         global EMIF_SDRAM_TIM_2_SHDW
 894         global EMIF_SDRAM_TIM_3_SHDW
 895         global EMIF_ZQ_CONFIG
 896
 897         mww $EMIF_SDRAM_TIM_1           0xeaaad4db
 898         mww $EMIF_SDRAM_TIM_1_SHDW      0xeaaad4db
 899
 900         mww $EMIF_SDRAM_TIM_2           0x266b7fda
 901         mww $EMIF_SDRAM_TIM_2_SHDW      0x266b7fda
 902
 903         mww $EMIF_SDRAM_TIM_3           0x107f8678
 904         mww $EMIF_SDRAM_TIM_3_SHDW      0x107f8678
 905
 906         mww $EMIF_ZQ_CONFIG             0x50074be4
 907 }
 908
 909 proc config_ddr_pm { } {
 910         global EMIF_PWR_MGMT_CTRL
 911         global EMIF_PWR_MGMT_CTRL_SHDW
 912         global EMIF_DLL_CALIB_CTRL
 913         global EMIF_DLL_CALIB_CTRL_SHDW
 914         global EMIF_TEMP_ALERT_CONFIG
 915
 916         mww $EMIF_PWR_MGMT_CTRL         0x00
 917         mww $EMIF_PWR_MGMT_CTRL_SHDW    0x00
 918         mww $EMIF_DLL_CALIB_CTRL        0x00050000
 919         mww $EMIF_DLL_CALIB_CTRL_SHDW   0x00050000
 920         mww $EMIF_TEMP_ALERT_CONFIG     0x00
 921 }
 922
 923 proc config_ddr_priority { } {
 924         global EMIF_PRI_COS_MAP
 925         global EMIF_CONNID_COS_1_MAP
 926         global EMIF_CONNID_COS_2_MAP
 927         global EMIF_RD_WR_EXEC_THRSH
 928         global COS_CONFIG
 929
 930         mww $EMIF_PRI_COS_MAP       0x00
 931         mww $EMIF_CONNID_COS_1_MAP  0x00
 932         mww $EMIF_CONNID_COS_2_MAP  0x0
 933         mww $EMIF_RD_WR_EXEC_THRSH  0x0405
 934         mww $COS_CONFIG             0x00ffffff
 935 }
 936
 937 proc config_ddr3 { SDRAM_CONFIG } {
 938         global CM_DLL_CTRL
 939         global EMIF_IODFT_TLGC
 940         global EMIF_RDWR_LVL_CTRL
 941         global EMIF_RDWR_LVL_RMP_CTRL
 942         global EMIF_SDRAM_CONFIG
 943         global EMIF_SDRAM_CONFIG_EXT
 944         global EMIF_SDRAM_REF_CTRL
 945         global EMIF_SDRAM_REF_CTRL_SHDW
 946         global EMIF_STATUS
 947         global EXT_PHY_CTRL_36
 948         global EXT_PHY_CTRL_36_SHDW
 949
 950         emif_prcm_clk_enable
 951         vtp_enable
 952
 953         set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
 954         mww $CM_DLL_CTRL $dll
 955         while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
 956
 957         config_ddr_ioctrl
 958
 959         mww $EMIF_SDRAM_CONFIG_EXT      0xc163
 960         mww $EMIF_IODFT_TLGC            0x2011
 961         mww $EMIF_IODFT_TLGC            0x2411
 962         mww $EMIF_IODFT_TLGC            0x2011
 963         mww $EMIF_SDRAM_REF_CTRL        0x80003000
 964
 965         config_ddr_phy
 966
 967         mww $EMIF_IODFT_TLGC            0x2011
 968         mww $EMIF_IODFT_TLGC            0x2411
 969         mww $EMIF_IODFT_TLGC            0x2011
 970
 971         config_ddr_timing
 972         config_ddr_pm
 973         config_ddr_priority
 974
 975         mww $EMIF_SDRAM_REF_CTRL        0x3000
 976         mww $EMIF_SDRAM_CONFIG          $SDRAM_CONFIG
 977
 978         mww $EMIF_SDRAM_REF_CTRL        0x0c30
 979         mww $EMIF_SDRAM_REF_CTRL_SHDW   0x0c30
 980
 981         sleep 10
 982
 983         set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
 984         mww $EXT_PHY_CTRL_36            $tmp
 985         mww $EXT_PHY_CTRL_36_SHDW       $tmp
 986
 987         mww $EMIF_RDWR_LVL_RMP_CTRL     0x80000000
 988         mww $EMIF_RDWR_LVL_CTRL         0x80000000
 989
 990         while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
 991
 992         if { [ mrw $EMIF_STATUS ]  & 0x70 } {
 993                 error "DDR3 Hardware Leveling incomplete!!!"
 994         }
 995 }
 996
 997 proc init_platform { SDRAM_CONFIG } {
 998         config_opp100
 999         config_ddr3 $SDRAM_CONFIG
1000 }
1001
1002 $_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
1003 $_TARGETNAME configure -event reset-end { disable_watchdog }