1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Altera cyclone V SoC family, 5Cxxx
6 if { [info exists CHIPNAME] } {
7 set _CHIPNAME $CHIPNAME
12 # CoreSight Debug Access Port
13 if { [info exists DAP_TAPID] } {
14 set _DAP_TAPID $DAP_TAPID
16 set _DAP_TAPID 0x4ba00477
19 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
20 -expected-id $_DAP_TAPID
22 # Subsidiary TAP: fpga
23 if { [info exists FPGA_TAPID] } {
24 set _FPGA_TAPID $FPGA_TAPID
26 set _FPGA_TAPID 0x02d020dd
28 jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
35 # GDB target: Cortex-A9, using DAP, configuring only one core
36 # Base addresses of cores:
40 # Slow speed to be sure it will work
43 set _TARGETNAME1 $_CHIPNAME.cpu.0
44 set _TARGETNAME2 $_CHIPNAME.cpu.1
47 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
48 target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
49 -coreid 0 -dbgbase 0x80110000
51 $_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
52 $_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
56 #target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
57 # -coreid 1 -dbgbase 0x80112000
59 #$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
60 #$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
62 proc cycv_dbginit {target} {
63 # General Cortex-A8/A9 debug initialisation