2 # Texas Instruments XDS100v2
4 # http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features
6 # Detailed documentation is available only as CPLD verilog source code
7 # to the registered TI users.
11 ftdi vid_pid 0x0403 0xa6d0 0x0403 0x6010
13 ftdi layout_init 0x0038 0x597b
16 # 4000 0 > CPLD loopback (all target side pins high-Z)
17 # 2000 z < !( cable connected ) (open drain on CPLD side for $reasons)
20 # 800 0 > PWR_RST = clear power-loss flag on rising edge
21 # 400 z < !( power-loss flag )
35 # As long as the power-loss flag is set, all target-side pins are
36 # high-Z except the EMU-pins for which the opposite holds unless
39 # To use wait-in-reset, drive EMU0 low at power-on reset. If the
40 # target normally reuses EMU0 for other purposes, clear EMU_EN to
41 # keep the EMU pins high-Z until the target is power-cycled.
43 # The LED only turns off at USB suspend, which is also the only way to
44 # set the power-loss flag manually. (Can be done in software e.g. by
45 # changing the USB configuration to zero.)
48 ftdi layout_signal nTRST -data 0x0010
49 ftdi layout_signal nSRST -oe 0x0100
50 ftdi layout_signal EMU_EN -data 0x0020
51 ftdi layout_signal EMU0 -oe 0x0040
52 ftdi layout_signal EMU1 -oe 0x1000
53 ftdi layout_signal PWR_RST -data 0x0800
54 ftdi layout_signal LOOPBACK -data 0x4000
56 echo "\nInfo : to use this adapter you MUST add ``init; ftdi set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\n"
57 # note: rising edge on PWR_RST is also needed after power-cycling the