1 # Copyright (C) 2015, 2020 Synopsys, Inc.
2 # Anton Kolesov <anton.kolesov@synopsys.com>
3 # Didin Evgeniy <didin@synopsys.com>
5 # SPDX-License-Identifier: GPL-2.0-or-later
7 # Things common to all ARCs
9 # It is assumed that target is already halted.
10 proc arc_common_reset { {target ""} } {
11 if { $target != "" } {
17 # 1. Interrupts are disabled (STATUS32.IE)
18 # 2. The status register flags are cleared.
19 # All fields, except the H bit, are set to 0 when the processor is Reset.
21 arc jtag set-aux-reg 0xA 0x1
23 # 3. The loop count, loop start, and loop end registers are cleared.
24 arc jtag set-core-reg 60 0
25 arc jtag set-aux-reg 0x2 0
26 arc jtag set-aux-reg 0x3 0
28 # Program execution begins at the address referenced by the four byte reset
29 # vector located at the interrupt vector base address, which is the first
30 # entry (offset 0x00) in the vector table.
31 set int_vector_base [arc jtag get-aux-reg 0x25]
33 mem2array start_pc 32 $int_vector_base 1
34 arc jtag set-aux-reg 0x6 $start_pc(0)
36 # It is OK to do uncached writes - register cache will be invalidated by
37 # the reset_assert() function.