1 # /* Peripheral and SRAM base address in the alias region */
2 set PERIPH_BB_BASE 0x42000000
3 set SRAM_BB_BASE 0x22000000
5 # /*Peripheral and SRAM base address in the bit-band region */
6 set SRAM_BASE 0x20000000
7 set PERIPH_BASE 0x40000000
9 # /*FSMC registers base address */
10 set FSMC_R_BASE 0xA0000000
12 # /*Peripheral memory map */
13 set APB1PERIPH_BASE [set PERIPH_BASE]
14 set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}]
15 set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}]
17 set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}]
18 set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}]
19 set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}]
20 set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}]
21 set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}]
22 set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}]
23 set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}]
24 set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}]
25 set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}]
26 set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}]
27 set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}]
28 set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}]
29 set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}]
30 set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}]
31 set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}]
32 set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}]
33 set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}]
34 set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}]
35 set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}]
36 set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}]
37 set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}]
39 set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}]
40 set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}]
41 set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}]
42 set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}]
43 set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}]
44 set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}]
45 set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}]
46 set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}]
47 set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}]
48 set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}]
49 set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}]
50 set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}]
51 set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}]
52 set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}]
53 set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}]
54 set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}]
56 set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}]
58 set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}]
59 set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}]
60 set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}]
61 set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}]
62 set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}]
63 set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}]
64 set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}]
65 set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}]
66 set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}]
67 set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}]
68 set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}]
69 set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}]
70 set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}]
71 set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}]
72 set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}]
73 set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}]
75 # /*Flash registers base address */
76 set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}]
77 # /*Flash Option Bytes base address */
78 set OB_BASE 0x1FFFF800
80 # /*FSMC Bankx registers base address */
81 set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}]
82 set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}]
83 set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}]
84 set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}]
85 set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}]
87 # /*Debug MCU registers base address */
88 set DBGMCU_BASE 0xE0042000
90 # /*System Control Space memory map */
91 set SCS_BASE 0xE000E000
93 set SysTick_BASE [expr {$SCS_BASE + 0x0010}]
94 set NVIC_BASE [expr {$SCS_BASE + 0x0100}]
95 set SCB_BASE [expr {$SCS_BASE + 0x0D00}]