27 proc sam9_smc_config { cs smc_config } {
28 ;# Setup Register for CS n
29 set AT91_SMC_SETUP [expr ($::AT91_SMC + 0x00 + ((cs)*0x10))]
30 set val [expr ($smc_config(nwe_setup) << 0)]
31 set val [expr ($val | $smc_config(ncs_write_setup) << 8]
32 set val [expr ($val | $smc_config(nrd_setup)) << 16]
33 set val [expr ($val | $smc_config(ncs_read_setup) << 24]
34 mww $AT91_SMC_SETUP $val
36 ;# Pulse Register for CS n
37 set AT91_SMC_PULSE [expr ($::AT91_SMC + 0x04 + ((cs)*0x10))]
38 set val [expr ($smc_config(nwe_pulse) << 0)]
39 set val [expr ($val | $smc_config(ncs_write_pulse) << 8]
40 set val [expr ($val | $smc_config(nrd_pulse) << 16]
41 set val [expr ($val | $smc_config(ncs_read_pulse) << 24]
42 mww $AT91_SMC_PULSE $val
44 ;# Cycle Register for CS n
45 set AT91_SMC_CYCLE [expr ($::AT91_SMC + 0x08 + ((cs)*0x10))]
46 set val [expr ($smc_config(write_cycle) << 0)]
47 set val [expr ($val | $smc_config(read_cycle) << 16]
48 mww $AT91_SMC_CYCLE $val
50 ;# Mode Register for CS n
51 set AT91_SMC_MODE [expr ($::AT91_SMC + 0x0c + ((cs)*0x10))]
52 set val [expr ($smc_config(mode) << 0)]
53 set val [expr ($val | $smc_config(tdf_cycles) << 16]
54 mww $AT91_SMC_MODE $val