1 # SPDX-License-Identifier: GPL-2.0-or-later
29 proc sam9_smc_config { cs smc_config } {
30 ;# Setup Register for CS n
31 set AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}]
32 set val [expr {$smc_config(nwe_setup) << 0}]
33 set val [expr {$val | $smc_config(ncs_write_setup) << 8}]
34 set val [expr {$val | $smc_config(nrd_setup)) << 16}]
35 set val [expr {$val | $smc_config(ncs_read_setup) << 24}]
36 mww $AT91_SMC_SETUP $val
38 ;# Pulse Register for CS n
39 set AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}]
40 set val [expr {$smc_config(nwe_pulse) << 0}]
41 set val [expr {$val | $smc_config(ncs_write_pulse) << 8}]
42 set val [expr {$val | $smc_config(nrd_pulse) << 16}]
43 set val [expr {$val | $smc_config(ncs_read_pulse) << 24}]
44 mww $AT91_SMC_PULSE $val
46 ;# Cycle Register for CS n
47 set AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}]
48 set val [expr {$smc_config(write_cycle) << 0}]
49 set val [expr {$val | $smc_config(read_cycle) << 16}]
50 mww $AT91_SMC_CYCLE $val
52 ;# Mode Register for CS n
53 set AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}]
54 set val [expr {$smc_config(mode) << 0}]
55 set val [expr {$val | $smc_config(tdf_cycles) << 16}]
56 mww $AT91_SMC_MODE $val