2 # SDRAM Controller (SDRAMC) registers
3 set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
4 set AT91_SDRAMC_MODE [expr {0xf << 0}] ;# Command Mode
5 set AT91_SDRAMC_MODE_NORMAL 0
6 set AT91_SDRAMC_MODE_NOP 1
7 set AT91_SDRAMC_MODE_PRECHARGE 2
8 set AT91_SDRAMC_MODE_LMR 3
9 set AT91_SDRAMC_MODE_REFRESH 4
10 set AT91_SDRAMC_MODE_EXT_LMR 5
11 set AT91_SDRAMC_MODE_DEEP 6
13 set AT91_SDRAMC_TR [expr {$AT91_SDRAMC + 0x04}] ;# SDRAM Controller Refresh Timer Register
14 set AT91_SDRAMC_COUNT [expr {0xfff << 0}] ;# Refresh Timer Counter
16 set AT91_SDRAMC_CR [expr {$AT91_SDRAMC + 0x08}] ;# SDRAM Controller Configuration Register
17 set AT91_SDRAMC_NC [expr {3 << 0}] ;# Number of Column Bits
18 set AT91_SDRAMC_NC_8 [expr {0 << 0}]
19 set AT91_SDRAMC_NC_9 [expr {1 << 0}]
20 set AT91_SDRAMC_NC_10 [expr {2 << 0}]
21 set AT91_SDRAMC_NC_11 [expr {3 << 0}]
22 set AT91_SDRAMC_NR [expr {3 << 2}] ;# Number of Row Bits
23 set AT91_SDRAMC_NR_11 [expr {0 << 2}]
24 set AT91_SDRAMC_NR_12 [expr {1 << 2}]
25 set AT91_SDRAMC_NR_13 [expr {2 << 2}]
26 set AT91_SDRAMC_NB [expr {1 << 4}] ;# Number of Banks
27 set AT91_SDRAMC_NB_2 [expr {0 << 4}]
28 set AT91_SDRAMC_NB_4 [expr {1 << 4}]
29 set AT91_SDRAMC_CAS [expr {3 << 5}] ;# CAS Latency
30 set AT91_SDRAMC_CAS_1 [expr {1 << 5}]
31 set AT91_SDRAMC_CAS_2 [expr {2 << 5}]
32 set AT91_SDRAMC_CAS_3 [expr {3 << 5}]
33 set AT91_SDRAMC_DBW [expr {1 << 7}] ;# Data Bus Width
34 set AT91_SDRAMC_DBW_32 [expr {0 << 7}]
35 set AT91_SDRAMC_DBW_16 [expr {1 << 7}]
36 set AT91_SDRAMC_TWR [expr {0xf << 8}] ;# Write Recovery Delay
37 set AT91_SDRAMC_TRC [expr {0xf << 12}] ;# Row Cycle Delay
38 set AT91_SDRAMC_TRP [expr {0xf << 16}] ;# Row Precharge Delay
39 set AT91_SDRAMC_TRCD [expr {0xf << 20}] ;# Row to Column Delay
40 set AT91_SDRAMC_TRAS [expr {0xf << 24}] ;# Active to Precharge Delay
41 set AT91_SDRAMC_TXSR [expr {0xf << 28}] ;# Exit Self Refresh to Active Delay
43 set AT91_SDRAMC_LPR [expr {$AT91_SDRAMC + 0x10}] ;# SDRAM Controller Low Power Register
44 set AT91_SDRAMC_LPCB [expr {3 << 0}] ;# Low-power Configurations
45 set AT91_SDRAMC_LPCB_DISABLE 0
46 set AT91_SDRAMC_LPCB_SELF_REFRESH 1
47 set AT91_SDRAMC_LPCB_POWER_DOWN 2
48 set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
49 set AT91_SDRAMC_PASR [expr {7 << 4}] ;# Partial Array Self Refresh
50 set AT91_SDRAMC_TCSR [expr {3 << 8}] ;# Temperature Compensated Self Refresh
51 set AT91_SDRAMC_DS [expr {3 << 10}] ;# Drive Strength
52 set AT91_SDRAMC_TIMEOUT [expr {3 << 12}] ;# Time to define when Low Power Mode is enabled
53 set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr {0 << 12}]
54 set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr {1 << 12}]
55 set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr {2 << 12}]
57 set AT91_SDRAMC_IER [expr {$AT91_SDRAMC + 0x14}] ;# SDRAM Controller Interrupt Enable Register
58 set AT91_SDRAMC_IDR [expr {$AT91_SDRAMC + 0x18}] ;# SDRAM Controller Interrupt Disable Register
59 set AT91_SDRAMC_IMR [expr {$AT91_SDRAMC + 0x1C}] ;# SDRAM Controller Interrupt Mask Register
60 set AT91_SDRAMC_ISR [expr {$AT91_SDRAMC + 0x20}] ;# SDRAM Controller Interrupt Status Register
61 set AT91_SDRAMC_RES [expr {1 << 0}] ;# Refresh Error Status
63 set AT91_SDRAMC_MDR [expr {$AT91_SDRAMC + 0x24}] ;# SDRAM Memory Device Register
64 set AT91_SDRAMC_MD [expr {3 << 0}] ;# Memory Device Type
65 set AT91_SDRAMC_MD_SDRAM 0
66 set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1