1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.
4 # http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html
6 # This is for using the onboard STLINK
7 source [find interface/stlink.cfg]
9 transport select hla_swd
11 # increase working area to 96KB
12 set WORKAREASIZE 0x18000
18 source [find target/stm32l4x.cfg]
20 # OCTOSPI initialization
22 proc octospi_init { octo } {
24 mmw 0x4002104C 0x001001FF 0 ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
25 mmw 0x40021050 0x00000300 0 ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
26 mmw 0x40021058 0x10000000 0 ;# RCC_APB1ENR1 |= PWREN (enable clock)
27 sleep 1 ;# Wait for clock startup
29 mmw 0x40007004 0x00000200 0 ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
31 mww 0x50061C04 0x07050333 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2
32 mww 0x50061C08 0x03010111 ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
34 # PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5
35 # PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0
37 # PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
38 # PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V
40 # Port A: PA07:AF10:V, PA06:AF10:V
41 mmw 0x48000000 0x0000A000 0x00005000 ;# MODER
42 mmw 0x48000008 0x0000F000 0x00000000 ;# OSPEEDR
43 mmw 0x4800000C 0x00000000 0x0000F000 ;# PUPDR
44 mmw 0x48000020 0xAA000000 0x55000000 ;# AFRL
46 mmw 0x48000800 0x00000080 0x00000040 ;# MODER
47 mmw 0x48000808 0x000000C0 0x00000000 ;# OSPEEDR
48 mmw 0x4800080C 0x00000000 0x000000C0 ;# PUPDR
49 mmw 0x48000820 0x0000A000 0x00005000 ;# AFRL
50 # Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V
51 mmw 0x48000C00 0x00008A00 0x00004500 ;# MODER
52 mmw 0x48000C08 0x0000CF00 0x00000000 ;# OSPEEDR
53 mmw 0x48000C0C 0x00000000 0x0000CF00 ;# PUPDR
54 mmw 0x48000C20 0xA0AA0000 0x50550000 ;# AFRL
55 # Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
56 mmw 0x48001000 0x0AA00000 0x05500000 ;# MODER
57 mmw 0x48001008 0x0FF00000 0x00000000 ;# OSPEEDR
58 mmw 0x4800100C 0x00000000 0x0FF00000 ;# PUPDR
59 mmw 0x48001024 0x00AAAA00 0x00555500 ;# AFRH
61 mmw 0x48001800 0x00002000 0x00001000 ;# MODER
62 mmw 0x48001808 0x00003000 0x00000000 ;# OSPEEDR
63 mmw 0x4800180C 0x00000000 0x00003000 ;# PUPDR
64 mmw 0x48001820 0x03000000 0x0C000000 ;# AFRL
66 # PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5
67 # PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0
69 # PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
70 # PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
72 # Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V
73 mmw 0x48001400 0x020002AA 0x01000155 ;# MODER
74 mmw 0x48001408 0x030003FF 0x00000000 ;# OSPEEDR
75 mmw 0x4800140C 0x00000000 0x030003FF ;# PUPDR
76 mmw 0x48001420 0x00055555 0x000AAAAA ;# AFRL
77 mmw 0x48001424 0x00050000 0x000A0000 ;# AFRH
78 # Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V
79 mmw 0x48001800 0x0228000A 0x01140005 ;# MODER
80 mmw 0x48001808 0x033C000F 0x00000000 ;# OSPEEDR
81 mmw 0x4800180C 0x00000000 0x033C000F ;# PUPDR
82 mmw 0x48001820 0x00000055 0x000000AA ;# AFRL
83 mmw 0x48001824 0x00050550 0x000A0AA0 ;# AFRH
85 # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
86 mww 0xA0001130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
87 mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
88 mww 0xA0001008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
89 mww 0xA000100C 0x00000001 ;# OCTOSPI_DCR2: PRESCALER=1
91 mww 0xA0001108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
92 mww 0xA0001100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
93 mww 0xA0001110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B
96 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
97 stmqspi cmd $a 0 0x06 ;# Write Enable
98 stmqspi cmd $a 1 0x05 ;# Read Status Register
99 stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
101 # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
102 mww 0xA0001000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
103 mww 0xA0001108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
104 mww 0xA0001100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
105 mww 0xA0001110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read
107 flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values
109 stmqspi cmd $a 0 0x06 ;# Write Enable
110 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
111 stmqspi cmd $a 0 0x04 ;# Write Disable
112 stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
113 stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
117 $_TARGETNAME configure -event reset-init {
118 mmw 0x40022000 0x00000003 0x0000000C ;# 3 WS for 72 MHz HCLK
120 mmw 0x40021000 0x00000100 0x00000000 ;# HSI on
121 mww 0x4002100C 0x01002432 ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
122 mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1
123 mmw 0x40021000 0x01000000 0x00000000 ;# PLL on
125 mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL