1 # This is an STM32L476G discovery board with a single STM32L476VGT6 chip.
2 # http://www.st.com/en/evaluation-tools/32l476gdiscovery.html
4 # This is for using the onboard STLINK
5 source [find interface/stlink.cfg]
7 transport select hla_swd
9 # increase working area to 96KB
10 set WORKAREASIZE 0x18000
15 source [find target/stm32l4x.cfg]
17 # QUADSPI initialization
20 mmw 0x4002104C 0x000001FF 0 ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
21 mmw 0x40021050 0x00000100 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
22 sleep 1 ;# Wait for clock startup
24 # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
26 # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
28 # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
29 mmw 0x48001000 0xAAA00000 0x55500000 ;# MODER
30 mmw 0x48001008 0xFFF00000 0x00000000 ;# OSPEEDR
31 mmw 0x48001024 0xAAAAAA00 0x55555500 ;# AFRH
33 mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
34 mww 0xA0001000 0x01500008 ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
35 mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
36 mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
38 # memory-mapped read mode with 3-byte addresses
39 mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
42 $_TARGETNAME configure -event reset-init {
43 mmw 0x40022000 0x00000004 0x00000003 ;# 4 WS for 72 MHz HCLK
45 mmw 0x40021000 0x00000100 0x00000000 ;# HSI on
46 mww 0x4002100C 0x01002432 ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
47 mww 0x40021008 0x00008001 ;# always HSI, APB1: /1, APB2: /1
48 mmw 0x40021000 0x01000000 0x00000000 ;# PLL on
50 mmw 0x40021008 0x00000003 0x00000000 ;# switch to PLL