1 # stm32h754i-disco and stm32h750b-dk dual quad qspi.
3 # QUADSPI initialization
5 proc qspi_init { qpi } {
7 mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
8 mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
9 sleep 1 ;# Wait for clock startup
11 # PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
12 # PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
14 # PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
15 # PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
18 mmw 0x58020C00 0x00800000 0x00400000 ;# MODER
19 mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR
20 mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH
21 # Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
22 mmw 0x58021400 0x0028A000 0x00145000 ;# MODER
23 mmw 0x58021408 0x003CF000 0x00000000 ;# OSPEEDR
24 mmw 0x58021420 0x99000000 0x66000000 ;# AFRL
25 mmw 0x58021424 0x000009A0 0x00000650 ;# AFRH
26 # Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
27 mmw 0x58021800 0x20082000 0x10041000 ;# MODER
28 mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR
29 mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
30 mmw 0x58021824 0x09000090 0x06000060 ;# AFRH
31 # Port H: PH03:AF09:V, PH02:AF09:V
32 mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER
33 mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR
34 mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL
36 # correct FSIZE is 0x1A, however, this causes trouble when
37 # reading the last bytes at end of bank in *memory mapped* mode
39 # for dual flash mode 2 * mt25ql512
40 mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
41 mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
43 mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
44 mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
45 mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
48 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
49 mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
54 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
55 mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
58 # Configure dummy clocks via volatile configuration register
59 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
60 mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
61 mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
62 mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
66 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
67 mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
70 # Enable QPI mode via enhanced volatile configuration register
71 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
72 mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
73 mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
74 mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
78 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
79 mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
82 # memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
83 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
84 mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
86 # memory-mapped read mode with 4-byte addresses
87 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
88 mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ