1 # This is an STM32F746G discovery board with a single STM32F746NGH6 chip.
2 # http://www.st.com/en/evaluation-tools/32f746gdiscovery.html
4 # This is for using the onboard STLINK
5 source [find interface/stlink.cfg]
7 transport select hla_swd
9 # increase working area to 256KB
10 set WORKAREASIZE 0x40000
15 source [find target/stm32f7x.cfg]
17 # QUADSPI initialization
20 mmw 0x40023830 0x000007FF 0 ;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)
21 mmw 0x40023838 0x00000002 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
22 sleep 1 ;# Wait for clock startup
24 # PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0
26 # PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V
28 # Port B: PB06:AF10:V, PB02:AF09:V
29 mmw 0x40020400 0x00002020 0x00001010 ;# MODER
30 mmw 0x40020408 0x00003030 0x00000000 ;# OSPEEDR
31 mmw 0x40020420 0x0A000900 0x05000600 ;# AFRL
33 # Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V
34 mmw 0x40020C00 0x0A800000 0x05400000 ;# MODER
35 mmw 0x40020C08 0x0FC00000 0x00000000 ;# OSPEEDR
36 mmw 0x40020C24 0x00999000 0x00666000 ;# AFRH
39 mmw 0x40021000 0x00000020 0x00000010 ;# MODER
40 mmw 0x40021008 0x00000030 0x00000000 ;# OSPEEDR
41 mmw 0x40021020 0x00000900 0x00000600 ;# AFRL
43 mww 0xA0001030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
44 mww 0xA0001000 0x03500008 ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
45 mww 0xA0001004 0x00170100 ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
46 mmw 0xA0001000 0x00000001 0 ;# QUADSPI_CR: EN=1
49 mww 0xA0001014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
52 # memory-mapped read mode with 3-byte addresses
53 mww 0xA0001014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
56 $_TARGETNAME configure -event reset-init {
57 mww 0x40023C00 0x00000006 ;# 6 WS for 192 MHz HCLK
59 mww 0x40023804 0x24003008 ;# 192 MHz: PLLM=8, PLLN=192, PLLP=2
60 mww 0x40023808 0x00009400 ;# APB1: /4, APB2: /2
61 mmw 0x40023800 0x01000000 0x00000000 ;# PLL on
63 mmw 0x40023808 0x00000002 0x00000000 ;# switch to PLL