1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # http://www.avalue.com.tw/products/RSC-W910.cfm
9 # Based on Nuvoton nuc910
10 source [find target/nuc910.cfg]
13 # reset only behaves correctly if we use srst_pulls_trst
15 reset_config trst_and_srst srst_pulls_trst
18 adapter srst delay 100
21 $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
23 set _FLASHNAME $_CHIPNAME.flash
24 flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
26 set _NANDNAME $_CHIPNAME.nand
27 nand device $_NANDNAME nuc910 $_TARGETNAME
33 $_TARGETNAME configure -event reset-start {adapter speed 1000}
35 $_TARGETNAME configure -event reset-init {
36 # switch on PLL for 200MHz operation
37 # running from 15MHz input clock
39 mww 0xB0000200 0x00000030 ;# CLKEN
40 mww 0xB0000204 0x00000f3c ;# CLKSEL
41 mww 0xB0000208 0x05007000 ;# CLKDIV
42 mww 0xB000020C 0x00004f24 ;# PLLCON0
43 mww 0xB0000210 0x00002b63 ;# PLLCON1
44 mww 0xB000000C 0x08817fa6 ;# MFSEL
47 # we are now running @ 200MHz
48 # enable all openocd speed tweaks
50 arm7_9 dcc_downloads enable
51 arm7_9 fast_memory_access enable
54 # map nor flash to 0x20000000
55 # map sdram to 0x00000000
57 mww 0xb0001000 0x000530c1 ;# EBICON
58 mww 0xb0001004 0x40030084 ;# ROMCON
59 mww 0xb0001008 0x000010ee ;# SDCONF0
60 mww 0xb000100C 0x00000000 ;# SDCONF1
61 mww 0xb0001010 0x0000015b ;# SDTIME0
62 mww 0xb0001014 0x0000015b ;# SDTIME1
63 mww 0xb0001018 0x00000000 ;# EXT0CON
64 mww 0xb000101C 0x00000000 ;# EXT1CON
65 mww 0xb0001020 0x00000000 ;# EXT2CON
66 mww 0xb0001024 0x00000000 ;# EXT3CON
67 mww 0xb000102c 0x00ff0048 ;# CKSKEW