1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Keil MCB1700 PCB with 1768
5 # Reset init script sets it to 100MHz
8 source [find target/lpc17xx.cfg]
11 set MCB1700_CCLK $CCLK
13 $_TARGETNAME configure -event reset-start {
14 # Start *real slow* as we do not know the
15 # state the boot rom left the clock in
19 # Set up 100MHz clock to CPU
20 $_TARGETNAME configure -event reset-init {
21 # PLL0CON: Disable PLL
22 mww 0x400FC080 0x00000000
24 mww 0x400FC08C 0x000000AA
26 mww 0x400FC08C 0x00000055
28 # CCLK=PLL/4 (=100 MHz)
29 mww 0x400FC104 0x00000003
30 # CLKSRCSEL: Clock source = internal RC oscillator
31 mww 0x400FC10C 0x00000000
33 # PLL0CFG: M=50,N=1 -> PLL=400 MHz
34 mww 0x400FC084 0x00000031
36 mww 0x400FC08C 0x000000AA
38 mww 0x400FC08C 0x00000055
41 mww 0x400FC080 0x00000001
43 mww 0x400FC08C 0x000000AA
45 mww 0x400FC08C 0x00000055
49 # PLL0CON: Connect PLL
50 mww 0x400FC080 0x00000003
52 mww 0x400FC08C 0x000000AA
54 mww 0x400FC08C 0x00000055
56 # Dividing CPU clock by 8 should be pretty conservative
60 adapter speed [expr {$MCB1700_CCLK / 8}]
62 # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
63 # "User Flash Mode" where interrupt vectors are _not_ remapped,
64 # and reside in flash instead).
66 # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
67 # Bit Symbol Value Description Reset
69 # 0 MAP Memory map control. 0
70 # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
71 # 1 User mode. The on-chip Flash memory is mapped to address 0.
72 # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
74 # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user