1 # SPDX-License-Identifier: GPL-2.0-or-later
3 #######################################
5 # http://www.denx-cs.de/?q=M53EVK #
6 # Author: Marek Vasut <marex@denx.de> #
7 # Based on imx53loco.cfg #
8 #######################################
10 # The DENX M53EVK has on-board JTAG adapter
11 source [find interface/ftdi/m53evk.cfg]
12 # The DENX M53EVK board has a single i.MX53 chip
13 source [find target/imx53.cfg]
14 # Helper for common memory read/modify/write procedures
15 source [find mem_helper.tcl]
17 echo "iMX53 M53EVK board lodaded."
20 reset_config trst_and_srst separate trst_open_drain srst_open_drain
25 $_TARGETNAME configure -event "reset-assert" {
30 $_TARGETNAME configure -event reset-init { m53evk_init }
32 global AIPS1_BASE_ADDR
33 set AIPS1_BASE_ADDR 0x53F00000
34 global AIPS2_BASE_ADDR
35 set AIPS2_BASE_ADDR 0x63F00000
37 proc m53evk_init { } {
42 echo "HW version [format %x [mrw 0x48]]"
47 ; # ARM errata ID #468414
48 set tR [arm mrc 15 0 1 0 1]
49 arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
58 ; #reg cpsr 0x000001D3
63 # L2CC Cache setup/invalidation/disable
65 ; #/* explicitly disable L2 cache */
66 ; #mrc 15, 0, r0, c1, c0, 1
67 set tR [arm mrc 15 0 1 0 1]
69 ; #mcr 15, 0, r0, c1, c0, 1
70 arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
72 ; #/* reconfigure L2 cache aux control reg */
73 ; #mov r0, #0xC0 /* tag RAM */
74 ; #add r0, r0, #0x4 /* data RAM */
75 ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
76 ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
77 ; #orr r0, r0, #(1 << 22) /* disable write allocate */
79 ; #mcr 15, 1, r0, c9, c0, 2
80 arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
84 # AIPS setup - Only setup MPROTx registers.
85 # The PACR default values are good.
87 ; # Set all MPROTx to be non-bufferable, trusted for R/W,
88 ; # not forced to user-mode.
89 global AIPS1_BASE_ADDR
90 global AIPS2_BASE_ADDR
94 mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
95 mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
96 mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
97 mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
102 proc init_clock { } {
103 global AIPS1_BASE_ADDR
104 global AIPS2_BASE_ADDR
105 set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
107 set CLKCTL_CBCDR 0x14
108 set CLKCTL_CBCMR 0x18
109 set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
110 set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
111 set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
112 set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
113 set CLKCTL_CSCMR1 0x1C
114 set CLKCTL_CDHIPR 0x48
115 set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
116 set CLKCTL_CSCDR1 0x24
119 ; # Switch ARM to step clock
120 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
124 setup_pll $PLL1_BASE_ADDR 800
125 setup_pll $PLL3_BASE_ADDR 400
127 ; # Switch peripheral to PLL3
128 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
129 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
130 while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
132 setup_pll $PLL2_BASE_ADDR 400
134 ; # Switch peripheral to PLL2
135 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
137 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
139 ; # change uart clk parent to pll2
140 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
142 ; # make sure change is effective
143 while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
145 setup_pll $PLL3_BASE_ADDR 216
147 setup_pll $PLL4_BASE_ADDR 455
149 ; # Set the platform clock dividers
150 mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
152 mww [expr {$CCM_BASE_ADDR + 0x10}] 0
154 ; # Switch ARM back to PLL 1.
155 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
158 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
160 ; # Restore the default values in the Gate registers
161 mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
162 mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
163 mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
164 mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
165 mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
166 mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
167 mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
168 mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
170 mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
172 ; # for cko - for ARM div by 8
173 mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
177 proc setup_pll { PLL_ADDR CLK } {
179 set PLL_DP_CONFIG 0x04
181 set PLL_DP_HFS_OP 0x1C
183 set PLL_DP_HFS_MFD 0x20
185 set PLL_DP_HFS_MFN 0x24
188 set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
189 set DP_MFD [expr {12 - 1}]
191 } elseif {$CLK == 850} {
192 set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
193 set DP_MFD [expr {48 - 1}]
195 } elseif {$CLK == 800} {
196 set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
197 set DP_MFD [expr {3 - 1}]
199 } elseif {$CLK == 700} {
200 set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
201 set DP_MFD [expr {24 - 1}]
203 } elseif {$CLK == 600} {
204 set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
205 set DP_MFD [expr {4 - 1}]
207 } elseif {$CLK == 665} {
208 set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
209 set DP_MFD [expr {96 - 1}]
211 } elseif {$CLK == 532} {
212 set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
213 set DP_MFD [expr {24 - 1}]
215 } elseif {$CLK == 455} {
216 set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
217 set DP_MFD [expr {48 - 1}]
219 } elseif {$CLK == 400} {
220 set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
221 set DP_MFD [expr {3 - 1}]
223 } elseif {$CLK == 216} {
224 set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
225 set DP_MFD [expr {4 - 1}]
228 error "Error (setup_dll): clock not found!"
231 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
232 mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
234 mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
235 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
237 mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
238 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
240 mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
241 mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
243 mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
244 while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
248 proc CPU_2_BE_32 { L } {
249 return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
253 # Device Configuration Data
256 mww 0x53fa86f4 0x00000000 ;# GRP_DDRMODE_CTL
257 mww 0x53fa8714 0x00000000 ;# GRP_DDRMODE
258 mww 0x53fa86fc 0x00000000 ;# GRP_DDRPKE
259 mww 0x53fa8724 0x04000000 ;# GRP_DDR_TYPE
261 mww 0x53fa872c 0x00300000 ;# GRP_B3DS
262 mww 0x53fa8554 0x00300000 ;# DRAM_DQM3
263 mww 0x53fa8558 0x00300040 ;# DRAM_SDQS3
265 mww 0x53fa8728 0x00300000 ;# GRP_B2DS
266 mww 0x53fa8560 0x00300000 ;# DRAM_DQM2
267 mww 0x53fa8568 0x00300040 ;# DRAM_SDQS2
269 mww 0x53fa871c 0x00300000 ;# GRP_B1DS
270 mww 0x53fa8594 0x00300000 ;# DRAM_DQM1
271 mww 0x53fa8590 0x00300040 ;# DRAM_SDQS1
273 mww 0x53fa8718 0x00300000 ;# GRP_B0DS
274 mww 0x53fa8584 0x00300000 ;# DRAM_DQM0
275 mww 0x53fa857c 0x00300040 ;# DRAM_SDQS0
277 mww 0x53fa8578 0x00300000 ;# DRAM_SDCLK_0
278 mww 0x53fa8570 0x00300000 ;# DRAM_SDCLK_1
280 mww 0x53fa8574 0x00300000 ;# DRAM_CAS
281 mww 0x53fa8588 0x00300000 ;# DRAM_RAS
282 mww 0x53fa86f0 0x00300000 ;# GRP_ADDDS
283 mww 0x53fa8720 0x00300000 ;# GRP_CTLDS
285 mww 0x53fa8564 0x00300040 ;# DRAM_SDODT1
286 mww 0x53fa8580 0x00300040 ;# DRAM_SDODT0
288 # Initialize DDR2 memory
289 mww 0x63fd9088 0x32383535
290 mww 0x63fd9090 0x40383538
291 mww 0x63fd907c 0x0136014d
292 mww 0x63fd9080 0x01510141
294 mww 0x63fd9018 0x00011740
295 mww 0x63fd9000 0xc3190000
296 mww 0x63fd900c 0x555952e3
297 mww 0x63fd9010 0xb68e8b63
298 mww 0x63fd9014 0x01ff00db
299 mww 0x63fd902c 0x000026d2
300 mww 0x63fd9030 0x009f0e21
301 mww 0x63fd9008 0x12273030
302 mww 0x63fd9004 0x0002002d
303 mww 0x63fd901c 0x00008032
304 mww 0x63fd901c 0x00008033
305 mww 0x63fd901c 0x00028031
306 mww 0x63fd901c 0x092080b0
307 mww 0x63fd901c 0x04008040
308 mww 0x63fd901c 0x0000803a
309 mww 0x63fd901c 0x0000803b
310 mww 0x63fd901c 0x00028039
311 mww 0x63fd901c 0x09208138
312 mww 0x63fd901c 0x04008048
313 mww 0x63fd9020 0x00001800
314 mww 0x63fd9040 0x04b80003
315 mww 0x63fd9058 0x00022227
316 mww 0x63fd901c 0x00000000