1 # Embedded Artists eval board for LPC2478
2 # http://www.embeddedartists.com/
4 # Target device: LPC2478
6 source [find target/lpc2478.cfg]
10 proc read_register {register} {
11 return [read_memory $register 32 1]
15 # Delays on reset lines
16 adapter srst delay 500
19 # Adaptive JTAG clocking through RTCK.
26 # A working area will help speeding the flash programming
27 $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
29 # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
30 flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
34 $_TARGETNAME configure -event reset-start {
35 # Back to the slow JTAG clock
39 $_TARGETNAME configure -event reset-init {
41 arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
42 arm7_9 fast_memory_access enable
45 mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value)
47 # Map the user flash to the vector table area (0x00...0x3F)
48 mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash
50 # Memory accelerator module
51 mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles
52 mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled
54 # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
55 mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
56 # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
57 # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
58 mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15
59 mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31
60 mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15
61 mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
62 # P4.25=WE, P4.30=CS0, P4.31=CS1
63 mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC
65 # Start PLL, then use faster JTAG clock
69 # 16-bit flash @ CS0 (SST39VF3201-70)
70 mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
71 mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0
72 mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0
73 mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0
74 mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0
75 mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0
76 mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0
81 # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
82 mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig
83 mww 0xFFE08030 0x00000001 ;# EMCDynamicRP
84 mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS
85 mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX
86 mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR
87 mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL
88 mww 0xFFE08044 0x00000001 ;# EMCDynamicWR
89 mww 0xFFE08048 0x00000005 ;# EMCDynamicRC
90 mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC
91 mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR
92 mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD
93 mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD
95 mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0
96 mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0
98 mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP
100 mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL
101 mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh
103 mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE
104 mdw 0xA0011000 1 ;# Set SDRAM mode register
105 mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
106 mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
109 $_TARGETNAME configure -event gdb-attach {
110 # Without this gdb-attach will first time as probe will fail
116 # Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
117 # Note: The PLL output runs at a frequency N times the desired CPU clock.
118 # It in unavoidable that the CPU clock drops down to (4 MHz/N) during
119 # the initialization!
121 # Note that if the PLL is already active at the time this script is
122 # called, the effective value of N is the value of CCLKCFG at that time!
125 # Disconnect PLL in case it is already connected
126 if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
127 # Disconnect it, but leave it enabled
128 # (This MUST be done in two steps)
129 mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
130 mww 0xE01FC08C 0x000000AA ;# PLLFEED
131 mww 0xE01FC08C 0x00000055 ;# PLLFEED
133 # Disable PLL (as it might already be enabled at this time!)
134 mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
135 mww 0xE01FC08C 0x000000AA ;# PLLFEED
136 mww 0xE01FC08C 0x00000055 ;# PLLFEED
138 # Setup PLL to generate 288 MHz from internal RC oscillator
139 mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
140 mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
141 mww 0xE01FC08C 0x000000AA ;# PLLFEED
142 mww 0xE01FC08C 0x00000055 ;# PLLFEED
143 mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
144 mww 0xE01FC08C 0x000000AA ;# PLLFEED
145 mww 0xE01FC08C 0x00000055 ;# PLLFEED
147 mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
148 mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
149 mww 0xE01FC08C 0x000000AA ;# PLLFEED
150 mww 0xE01FC08C 0x00000055 ;# PLLFEED