1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # https://www.dptechnics.com/en/products/dpt-board-v1.html
6 # JTAG is a 5 pin array located close to main module in following order:
11 # 5. GND The GND is located near letter G of word JTAG on board.
13 # Two RST pins are connected to:
15 # 2. GPIO11 this pin is located near letter R of word RST.
17 # To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
18 # with 10K resistor connected to V3.3 pin.
20 # This board is powered from micro USB connector. No real reset pin or button, for
21 # example RESET_L is available.
23 source [find target/atheros_ar9331.cfg]
25 $_TARGETNAME configure -event reset-init {
31 set ram_boot_address 0xa0000000
32 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
34 flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0