1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # DM365 EVM board -- Beta
4 # http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
5 # http://support.spectrumdigital.com/boards/evmdm365
7 source [find target/ti_dm365.cfg]
9 # NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
10 # connector, so it doesn't affect generation of the reset signal.
11 # Accordingly, resets require something else. ICEpick could do it;
12 # but its docs aren't generally available.
14 # At this writing, newer boards aren't available ... so assume no SRST.
15 # Also ICEpick docs aren't available ... so we must use watchdog reset,
16 # and hope the CPU isn't wedged or in a WFI loop (either of which can
17 # block access to CPU and thus watchdog registers).
19 reset_config trst_only
20 $_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
22 # SW5.1 routes CS0: NAND vs OneNAND.
23 # SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
24 # for boot-from-flash, those must agree with SW4.3:1 settings.
26 if { [info exists CS0MODE] } {
31 echo "WARNING: CS0 configuration not known"
32 proc cs0_setup {a_emif} {}
36 set a_emif [dict get $dm365 a_emif]
38 # As shipped: boot from NAND.
39 if { $CS0 == "NAND" } {
42 # NAND socket has two chipselects. Default MT29F16G08FAA chip
43 # has 1GByte on each one.
44 # NOTE: "hwecc4" here presumes that you're not updating anything
45 # that needs infix layout (e.g. UBL, old U-Boot, etc)
46 nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
47 nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
49 proc cs0_setup {a_emif} {
53 davinci_pinmux $dm365 2 0x00000016
55 # slow/pessimistic timings
56 set nand_timings 0x40400204
57 # fast (25% faster page reads)
58 #set nand_timings 0x0400008c
60 # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
61 mww [expr {$a_emif + 0x10}] $nand_timings
63 # NANDFCR -- CS0 has NAND
64 mww [expr {$a_emif + 0x60}] 0x01
71 } elseif { $CS0 == "OneNAND" } {
74 # No support for this OneNAND in OpenOCD (yet) or Linux ...
75 # REVISIT OneNAND timings not verified to work!
76 echo "WARNING -- OneNAND not yet tested!"
78 proc cs0_setup {a_emif} {
82 davinci_pinmux $dm365 2 0x00000055
84 # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
85 mww [expr {$a_emif + 0x10}] 0x00000001
87 # ONENANDCTRL -- CS0 has OneNAND, enable sync reads
88 mww [expr {$a_emif + 0x5c}] 0x0441
90 proc flashprobe {} { }
93 # NOTE: disable or replace this call to dm365evm_init if you're
94 # debugging new UBL/NANDboot code from SRAM.
95 $_TARGETNAME configure -event reset-init { dm365evm_init }
98 # This post-reset init is called when the MMU isn't active, all IRQs
99 # are disabled, etc. It should do most of what a UBL does, except for
100 # loading code (like U-Boot) into DRAM and running it.
102 proc dm365evm_init {} {
105 echo "Initialize DM365 EVM board"
107 # CLKIN = 24 MHz ... can't talk quickly to ARM yet
112 ########################
115 davinci_pinmux $dm365 0 0x00fd0000
116 davinci_pinmux $dm365 1 0x00145555
117 # mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
118 davinci_pinmux $dm365 3 0x375affff
119 davinci_pinmux $dm365 4 0x55556555
121 ########################
122 # PSC setup (minimal)
124 # DDR EMIF/13, AEMIF/14, UART0/19
130 # FIXME setup DDR2 (needs PLL)
132 ########################
135 set a_emif [dict get $dm365 a_emif]
138 mww [expr {$a_emif + 0x04}] 0xff
139 # CS0 == NAND or OneNAND
142 mww [expr {$a_emif + 0x14}] 0x00a00505