1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ################################################################################
4 # Atmel AT91SAM9260-EK eval board
6 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
8 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
9 # OSCSEL configured for external 32.768 kHz crystal
11 # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
13 ################################################################################
15 # We add to the minimal configuration.
16 source [find target/at91sam9260.cfg]
18 # By default S1 is open and this means that NTRST is not connected.
19 # The reset_config in target/at91sam9260.cfg is overridden here.
20 # (or S1 must be populated with a 0 Ohm resistor)
21 reset_config srst_only
23 $_TARGETNAME configure -event reset-start {
24 # At reset CPU runs at 32.768 kHz.
25 # JTAG Frequency must be 6 times slower if RCLK is not supported.
28 # RSTC_MR : enable user reset, MMU may be enabled... use physical address
29 mww phys 0xfffffd08 0xa5000501
32 $_TARGETNAME configure -event reset-init {
33 mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
35 mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
36 sleep 20 ;# wait 20 ms
37 mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
38 sleep 10 ;# wait 10 ms
39 mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
40 sleep 20 ;# wait 20 ms
41 mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
42 sleep 10 ;# wait 10 ms
43 mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
44 sleep 10 ;# wait 10 ms
46 # Increase JTAG Speed to 6 MHz if RCLK is not supported
49 arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
51 mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
52 mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
54 mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
56 mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
58 mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
60 mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
62 mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
78 mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
80 mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
82 mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us