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3 # Author: Gary Carlson (gcarlson@carlson-minot.com) #
4 # Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
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8 # FIXME use some standard target config, maybe create one from this
10 # source [find target/...cfg]
12 # Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of
13 # the AT91SAM9260 and shares the same tap ID as it.
15 set _CHIPNAME at91sam9g20
17 set _CPUTAPID 0x0792603f
19 # Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. In theory this script
20 # therefore should require "srst_only". With some J-Link debuggers at least, "srst_only" causes a temporary USB
21 # communication fault. This appears to be more likely attributed to an internal proprietary firmware quirk inside the
22 # dongle itself. Using "trst_and_srst" works fine, however. So if you can't beat them -- join them. If you are using
23 # something other the a J-Link dongle you may be able to change this back to "srst_only".
25 reset_config trst_and_srst
27 # Set up the CPU and generate a new jtag tap for AT91SAM9G20.
29 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
31 # Use caution changing the delays listed below. These seem to be
32 # affected by the board and type of JTAG adapter. A value of 200 ms seems
33 # to work reliably for the configuration listed in the file header above.
38 # Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
42 set _TARGETNAME $_CHIPNAME.cpu
43 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
45 # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
46 # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
47 # Both areas are 16 kB long.
49 #$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
50 $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
52 # If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
53 # AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
54 # some powerful features, we want to have a special function that handles "reset init". To do this we declare
55 # an event handler where these special activities can take place.
58 $_TARGETNAME configure -event reset-init {at91sam9g20_init}
60 # NandFlash configuration and definition
63 proc read_register {register} {
65 ocd_mem2array result 32 $register 1
69 proc at91sam9g20_init { } {
71 # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
72 # a number of steps that must be carefully performed. The process outline below follows the
73 # recommended procedure outlined in the AT91SAM9G20 technical manual.
75 # Several key and very important things to keep in mind:
76 # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
77 # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
78 # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
80 jtag_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
81 halt # Make sure processor is halted, or error will result in following steps.
82 mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
83 mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
85 # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
86 # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
88 mww 0xfffffc20 0x00004001
89 while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
91 # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
92 # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
94 mww 0xfffffc28 0x202a3f01
95 while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
97 # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
98 # Wait for MCKRDY signal from PMC_SR to assert.
100 mww 0xfffffc30 0x00000101
101 while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
103 # Now change PMC_MCKR register to select PLLA.
104 # Wait for MCKRDY signal from PMC_SR to assert.
106 mww 0xfffffc30 0x00001302
107 while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
109 # Processor and master clocks are now operating and stable at maximum frequency possible:
110 # -> MCLK = 132.096 MHz
111 # -> PCLK = 396.288 MHz
113 # Switch over to adaptive clocking.
117 # Enable faster DCC downloads.
119 arm7_9 dcc_downloads enable
121 # To be able to use external SDRAM, several peripheral configuration registers must
122 # be modified. The first change is made to PIO_ASR to select peripheral functions
123 # for D15 through D31. The second change is made to the PIO_PDR register to disable
124 # this for D15 through D31.
126 mww 0xfffff870 0xffff0000
127 mww 0xfffff804 0xffff0000
129 # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
130 # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
131 # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
133 mww 0xffffef1c 0x000100a
135 # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
136 # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
137 # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
139 mww 0xffffec30 0x00020002
140 mww 0xffffec34 0x04040404
141 mww 0xffffec38 0x00070007
142 mww 0xffffec3c 0x00030003
144 # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
148 # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
149 # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
150 # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
151 # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
152 # of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
154 # CAS latency = 3 cycles
161 # 9 column, 13 row, 4 banks
162 # refresh equal to or less then 7.8 us for commerical/industrial rated devices
164 # Thus SDRAM_CR = 0xa6339279
166 mww 0xffffea08 0xa6339279
168 # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
169 # the starting memory location for the SDRAM.
171 mww 0xffffea00 0x00000001
174 # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
175 # value into the starting memory location for the SDRAM.
177 mww 0xffffea00 0x00000002
180 # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
181 # zero values eight times into the starting memory location for the SDRAM.
193 # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
194 # the starting memory location for the SDRAM.
199 # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
200 # memory location for the SDRAM.
205 # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
207 mww 0xffffea04 0x0000039c