1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ################################################################################
4 # Atmel AT91SAM9261-EK eval board
5 ################################################################################
7 source [find mem_helper.tcl]
8 source [find target/at91sam9261.cfg]
9 uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
10 uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
11 uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
12 uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
14 # By default S1 is open and this means that NTRST is not connected.
15 # The reset_config in target/at91sam9261.cfg is overridden here.
16 # (or S1 must be populated with a 0 Ohm resistor)
17 reset_config srst_only
20 $_TARGETNAME configure -event gdb-attach { reset init }
21 $_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
22 $_TARGETNAME configure -event reset-start { at91sam9_reset_start }
24 proc at91sam9261ek_reset_init { } {
26 ;# for ppla at 199 Mhz
27 set config(master_pll_div) 15
28 set config(master_pll_mul) 162
30 ;# for ppla at 239 Mhz
31 ;# set master_pll_div 1
32 ;# set master_pll_mul 13
34 set val $::AT91_WDT_WDV ;# Counter Value
35 set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
36 set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
37 set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
38 set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
40 set config(wdt_mr_val) $val
42 ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
43 set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA
44 set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
46 ;# SDRAMC_CR - Configuration register
47 set val $::AT91_SDRAMC_NC_9
48 set val [expr {$val | $::AT91_SDRAMC_NR_13}]
49 set val [expr {$val | $::AT91_SDRAMC_NB_4}]
50 set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
51 set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
52 set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay
53 set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay
54 set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay
55 set val [expr {$val | (2 << 20)}] ;# Row to Column Delay
56 set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay
57 set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay
59 set config(sdram_cr_val) $val
61 set config(sdram_tr_val) 0x13c
63 set config(sdram_base) $::AT91_CHIPSELECT_1
64 at91sam9_reset_init $config