4 * main() ripped out of old stlink-hw.c
9 #include "stlink-common.h"
12 int main(int argc, char *argv[]) {
13 // set scpi lib debug level: 0 for no debug info, 10 for lots
14 const int scsi_verbose = 2;
20 "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
21 "\n*** Notice: The stlink firmware violates the USB standard.\n"
22 "*** If you plug-in the discovery's stlink, wait a several\n"
23 "*** minutes to let the kernel driver swallow the broken device.\n"
24 "*** Watch:\ntail -f /var/log/messages\n"
25 "*** This command sequence can shorten the waiting time and fix some issues.\n"
26 "*** Unplug the stlink and execute once as root:\n"
27 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
37 fputs("*** stlink access test ***\n", stderr);
38 DD(sl, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(),
41 struct stlink *sl = stlink_force_open(dev_name, scsi_verbose);
45 // we are in mass mode, go to swd
46 stlink_enter_swd_mode(sl);
47 stlink_current_mode(sl);
49 //----------------------------------------------------------------------
52 //stlink_force_debug(sl);
56 // core system control block
57 stlink_read_mem32(sl, 0xe000ed00, 4);
58 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
60 stlink_read_mem32(sl, 0xe000ed90, 4);
61 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
63 stlink_read_mem32(sl, 0xe000edf0, 4);
64 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
66 stlink_read_mem32(sl, 0x4001100c, 4);
67 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
70 // happy new year 2011: let blink all the leds
71 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
73 #define GPIOC 0x40011000 // port C
74 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
75 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
76 #define LED_BLUE (1<<8) // pin 8
77 #define LED_GREEN (1<<9) // pin 9
78 stlink_read_mem32(sl, GPIOC_CRH, 4);
79 uint32_t io_conf = read_uint32(sl->q_buf, 0);
80 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
82 // set: general purpose output push-pull, output mode, max speed 10 MHz.
83 write_uint32(sl->q_buf, 0x44444411);
84 stlink_write_mem32(sl, GPIOC_CRH, 4);
87 for (int i = 0; i < 100; i++) {
88 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
89 stlink_write_mem32(sl, GPIOC_ODR, 4);
90 /* stlink_read_mem32(sl, 0x4001100c, 4); */
91 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
95 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
98 write_uint32(sl->q_buf, io_conf); // set old state
102 // TODO rtfm: stlink doesn't have flash write routines
103 // writing to the flash area confuses the fw for the next read access
105 //stlink_read_mem32(sl, 0, 1024*6);
106 // flash 0x08000000 128kB
107 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
108 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
110 stlink_read_mem32(sl, 0x08000c00, 5);
111 stlink_read_mem32(sl, 0x08000c00, 4);
113 stlink_write_mem32(sl, 0x08000c00, 4);
114 stlink_read_mem32(sl, 0x08000c00, 256);
115 stlink_read_mem32(sl, 0x08000c00, 256);
118 // sram 0x20000000 8kB
119 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
121 stlink_write_mem8(sl, 0x20000000, 16);
124 stlink_write_mem8(sl, 0x20000000, 1);
125 stlink_write_mem8(sl, 0x20000001, 1);
126 stlink_write_mem8(sl, 0x2000000b, 3);
127 stlink_read_mem32(sl, 0x20000000, 16);
130 // a not aligned mem32 access doesn't work indeed
131 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
133 stlink_write_mem8(sl, 0x20000000, 32);
136 stlink_write_mem32(sl, 0x20000000, 1);
137 stlink_read_mem32(sl, 0x20000000, 16);
139 stlink_write_mem32(sl, 0x20000001, 1);
140 stlink_read_mem32(sl, 0x20000000, 16);
142 stlink_write_mem32(sl, 0x2000000b, 3);
143 stlink_read_mem32(sl, 0x20000000, 16);
146 stlink_write_mem32(sl, 0x20000000, 17);
147 stlink_read_mem32(sl, 0x20000000, 32);
150 // sram 0x20000000 8kB
151 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
153 stlink_write_mem8(sl, 0x20000000, 64);
154 stlink_read_mem32(sl, 0x20000000, 64);
157 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
158 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
159 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
162 stlink_read_all_regs(sl);
164 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
165 stlink_write_reg(sl, 0x12345678, 0);
166 stlink_read_reg(sl, 0);
167 stlink_read_all_regs(sl);
173 stlink_force_debug(sl);
176 #if 1 /* read the system bootloader */
177 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
178 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
180 #if 0 /* read the flash memory */
181 fputs("\n+++++++ read flash memory\n\n", stderr);
183 stlink_read_mem32(sl, 0x08000000, 4);
185 #if 0 /* flash programming */
186 fputs("\n+++++++ program flash memory\n\n", stderr);
187 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
189 #if 0 /* check file contents */
190 fputs("\n+++++++ check flash memory\n\n", stderr);
192 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
193 printf("_____ stlink_fcheck_flash() == %d\n", res);
197 fputs("\n+++++++ sram write and execute\n\n", stderr);
198 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
199 stlink_run_at(sl, sl->sram_base);
204 //----------------------------------------------------------------------
205 // back to mass mode, just in case ...
206 stlink_exit_debug_mode(sl);
207 stlink_current_mode(sl);
210 //fflush(stderr); fflush(stdout);