4 * main() ripped out of old stlink-hw.c
9 #include "stlink-common.h"
11 int main(int argc, char *argv[]) {
12 // set scpi lib debug level: 0 for no debug info, 10 for lots
17 "\nUsage: stlink-access-test [anything at all] ...\n"
18 "\n*** Notice: The stlink firmware violates the USB standard.\n"
19 "*** Because we just use libusb, we can just tell the kernel's\n"
20 "*** driver to simply ignore the device...\n"
21 "*** Unplug the stlink and execute once as root:\n"
22 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n",
29 stlink_t *sl = stlink_v1_open(99);
33 // we are in mass mode, go to swd
34 stlink_enter_swd_mode(sl);
35 stlink_current_mode(sl);
37 //----------------------------------------------------------------------
40 //stlink_force_debug(sl);
44 // core system control block
45 stlink_read_mem32(sl, 0xe000ed00, 4);
46 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
48 stlink_read_mem32(sl, 0xe000ed90, 4);
49 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
51 stlink_read_mem32(sl, 0xe000edf0, 4);
52 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
54 stlink_read_mem32(sl, 0x4001100c, 4);
55 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
58 // happy new year 2011: let blink all the leds
59 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
61 #define GPIOC 0x40011000 // port C
62 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
63 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
64 #define LED_BLUE (1<<8) // pin 8
65 #define LED_GREEN (1<<9) // pin 9
66 stlink_read_mem32(sl, GPIOC_CRH, 4);
67 uint32_t io_conf = read_uint32(sl->q_buf, 0);
68 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
70 // set: general purpose output push-pull, output mode, max speed 10 MHz.
71 write_uint32(sl->q_buf, 0x44444411);
72 stlink_write_mem32(sl, GPIOC_CRH, 4);
75 for (int i = 0; i < 100; i++) {
76 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
77 stlink_write_mem32(sl, GPIOC_ODR, 4);
78 /* stlink_read_mem32(sl, 0x4001100c, 4); */
79 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
83 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
86 write_uint32(sl->q_buf, io_conf); // set old state
90 // TODO rtfm: stlink doesn't have flash write routines
91 // writing to the flash area confuses the fw for the next read access
93 //stlink_read_mem32(sl, 0, 1024*6);
94 // flash 0x08000000 128kB
95 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
96 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
98 stlink_read_mem32(sl, 0x08000c00, 5);
99 stlink_read_mem32(sl, 0x08000c00, 4);
101 stlink_write_mem32(sl, 0x08000c00, 4);
102 stlink_read_mem32(sl, 0x08000c00, 256);
103 stlink_read_mem32(sl, 0x08000c00, 256);
106 // sram 0x20000000 8kB
107 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
109 stlink_write_mem8(sl, 0x20000000, 16);
112 stlink_write_mem8(sl, 0x20000000, 1);
113 stlink_write_mem8(sl, 0x20000001, 1);
114 stlink_write_mem8(sl, 0x2000000b, 3);
115 stlink_read_mem32(sl, 0x20000000, 16);
118 // a not aligned mem32 access doesn't work indeed
119 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
121 stlink_write_mem8(sl, 0x20000000, 32);
124 stlink_write_mem32(sl, 0x20000000, 1);
125 stlink_read_mem32(sl, 0x20000000, 16);
127 stlink_write_mem32(sl, 0x20000001, 1);
128 stlink_read_mem32(sl, 0x20000000, 16);
130 stlink_write_mem32(sl, 0x2000000b, 3);
131 stlink_read_mem32(sl, 0x20000000, 16);
134 stlink_write_mem32(sl, 0x20000000, 17);
135 stlink_read_mem32(sl, 0x20000000, 32);
138 // sram 0x20000000 8kB
139 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
141 stlink_write_mem8(sl, 0x20000000, 64);
142 stlink_read_mem32(sl, 0x20000000, 64);
145 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
146 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
147 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
150 stlink_read_all_regs(sl);
152 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
153 stlink_write_reg(sl, 0x12345678, 0);
154 stlink_read_reg(sl, 0);
155 stlink_read_all_regs(sl);
161 stlink_force_debug(sl);
164 #if 0 /* read the system bootloader */
165 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
166 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
168 #if 0 /* read the flash memory */
169 fputs("\n+++++++ read flash memory\n\n", stderr);
171 stlink_read_mem32(sl, 0x08000000, 4);
173 #if 0 /* flash programming */
174 fputs("\n+++++++ program flash memory\n\n", stderr);
175 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
177 #if 0 /* check file contents */
178 fputs("\n+++++++ check flash memory\n\n", stderr);
180 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
181 printf("_____ stlink_fcheck_flash() == %d\n", res);
185 fputs("\n+++++++ sram write and execute\n\n", stderr);
186 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
187 stlink_run_at(sl, sl->sram_base);
193 //----------------------------------------------------------------------
194 // back to mass mode, just in case ...
195 stlink_exit_debug_mode(sl);
196 stlink_current_mode(sl);
200 //fflush(stderr); fflush(stdout);