4 * main() ripped out of old stlink-hw.c
10 #include "stlink-common.h"
11 #include "uglylogging.h"
13 static void __attribute__((unused)) mark_buf(stlink_t *sl) {
14 memset(sl->q_buf, 0, sizeof(sl->q_buf));
24 sl->q_buf[1024 * 6 - 1] = 0x42; //6kB
25 sl->q_buf[1024 * 8 - 1] = 0x42; //8kB
29 int main(int argc, char *argv[]) {
30 /* Avoid unused parameter warning */
32 // set scpi lib debug level: 0 for no debug info, 10 for lots
37 "\nUsage: stlink-access-test [anything at all] ...\n"
38 "\n*** Notice: The stlink firmware violates the USB standard.\n"
39 "*** Because we just use libusb, we can just tell the kernel's\n"
40 "*** driver to simply ignore the device...\n"
41 "*** Unplug the stlink and execute once as root:\n"
42 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n",
49 stlink_t *sl = stlink_v1_open(99, 1);
53 // we are in mass mode, go to swd
54 stlink_enter_swd_mode(sl);
55 stlink_current_mode(sl);
57 //----------------------------------------------------------------------
60 //stlink_force_debug(sl);
63 // core system control block
64 stlink_read_mem32(sl, 0xe000ed00, 4);
65 DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0));
67 stlink_read_mem32(sl, 0xe000ed90, 4);
68 DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0));
71 stlink_read_mem32(sl, 0xe000edf0, 4);
72 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
74 stlink_read_mem32(sl, 0x4001100c, 4);
75 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
78 // happy new year 2011: let blink all the leds
79 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
81 #define GPIOC 0x40011000 // port C
82 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
83 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
84 #define LED_BLUE (1<<8) // pin 8
85 #define LED_GREEN (1<<9) // pin 9
86 stlink_read_mem32(sl, GPIOC_CRH, 4);
87 uint32_t io_conf = read_uint32(sl->q_buf, 0);
88 DLOG("GPIOC_CRH = 0x%08x\n", io_conf);
90 // set: general purpose output push-pull, output mode, max speed 10 MHz.
91 write_uint32(sl->q_buf, 0x44444411);
92 stlink_write_mem32(sl, GPIOC_CRH, 4);
94 memset(sl->q_buf, 0, sizeof(sl->q_buf));
95 for (int i = 0; i < 100; i++) {
96 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
97 stlink_write_mem32(sl, GPIOC_ODR, 4);
98 /* stlink_read_mem32(sl, 0x4001100c, 4); */
99 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
102 memset(sl->q_buf, 0, sizeof(sl->q_buf));
103 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
106 write_uint32(sl->q_buf, io_conf); // set old state
110 // TODO rtfm: stlink doesn't have flash write routines
111 // writing to the flash area confuses the fw for the next read access
113 //stlink_read_mem32(sl, 0, 1024*6);
114 // flash 0x08000000 128kB
115 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
116 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
118 stlink_read_mem32(sl, 0x08000c00, 5);
119 stlink_read_mem32(sl, 0x08000c00, 4);
121 stlink_write_mem32(sl, 0x08000c00, 4);
122 stlink_read_mem32(sl, 0x08000c00, 256);
123 stlink_read_mem32(sl, 0x08000c00, 256);
126 // sram 0x20000000 8kB
127 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
128 memset(sl->q_buf, 0, sizeof(sl->q_buf));
130 //stlink_write_mem8(sl, 0x20000000, 16);
132 //stlink_write_mem8(sl, 0x20000000, 1);
133 //stlink_write_mem8(sl, 0x20000001, 1);
134 stlink_write_mem8(sl, 0x2000000b, 3);
135 stlink_read_mem32(sl, 0x20000000, 16);
138 // a not aligned mem32 access doesn't work indeed
139 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
140 memset(sl->q_buf, 0, sizeof(sl->q_buf));
142 stlink_write_mem32(sl, 0x20000000, 1);
143 stlink_read_mem32(sl, 0x20000000, 16);
145 stlink_write_mem32(sl, 0x20000001, 1);
146 stlink_read_mem32(sl, 0x20000000, 16);
148 stlink_write_mem32(sl, 0x2000000b, 3);
149 stlink_read_mem32(sl, 0x20000000, 16);
152 stlink_write_mem32(sl, 0x20000000, 17);
153 stlink_read_mem32(sl, 0x20000000, 32);
156 // sram 0x20000000 8kB
157 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
158 memset(sl->q_buf, 0, sizeof(sl->q_buf));
160 stlink_write_mem8(sl, 0x20000000, 64);
161 stlink_read_mem32(sl, 0x20000000, 64);
164 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
165 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
166 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
170 stlink_read_all_regs(sl, ®s);
172 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
173 stlink_write_reg(sl, 0x12345678, 0);
174 stlink_read_reg(sl, 0, ®s);
175 stlink_read_all_regs(sl, ®s);
181 stlink_force_debug(sl);
184 #if 0 /* read the system bootloader */
185 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
186 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
188 #if 0 /* read the flash memory */
189 fputs("\n+++++++ read flash memory\n\n", stderr);
191 stlink_read_mem32(sl, 0x08000000, 4);
193 #if 0 /* flash programming */
194 fputs("\n+++++++ program flash memory\n\n", stderr);
195 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
197 #if 0 /* check file contents */
198 fputs("\n+++++++ check flash memory\n\n", stderr);
200 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
201 printf("_____ stlink_fcheck_flash() == %d\n", res);
205 fputs("\n+++++++ sram write and execute\n\n", stderr);
206 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
207 stlink_run_at(sl, sl->sram_base);
213 //----------------------------------------------------------------------
214 // back to mass mode, just in case ...
215 stlink_exit_debug_mode(sl);
216 stlink_current_mode(sl);
220 //fflush(stderr); fflush(stdout);