4 * main() ripped out of old stlink-hw.c
9 #include "stlink-common.h"
11 int main(int argc, char *argv[]) {
12 // set scpi lib debug level: 0 for no debug info, 10 for lots
13 const int scsi_verbose = 2;
19 "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
20 "\n*** Notice: The stlink firmware violates the USB standard.\n"
21 "*** If you plug-in the discovery's stlink, wait a several\n"
22 "*** minutes to let the kernel driver swallow the broken device.\n"
23 "*** Watch:\ntail -f /var/log/messages\n"
24 "*** This command sequence can shorten the waiting time and fix some issues.\n"
25 "*** Unplug the stlink and execute once as root:\n"
26 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
36 fputs("*** stlink access test ***\n", stderr);
37 fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(),
40 stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose);
44 // we are in mass mode, go to swd
45 stlink_enter_swd_mode(sl);
46 stlink_current_mode(sl);
48 //----------------------------------------------------------------------
51 //stlink_force_debug(sl);
55 // core system control block
56 stlink_read_mem32(sl, 0xe000ed00, 4);
57 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
59 stlink_read_mem32(sl, 0xe000ed90, 4);
60 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
62 stlink_read_mem32(sl, 0xe000edf0, 4);
63 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
65 stlink_read_mem32(sl, 0x4001100c, 4);
66 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
69 // happy new year 2011: let blink all the leds
70 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
72 #define GPIOC 0x40011000 // port C
73 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
74 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
75 #define LED_BLUE (1<<8) // pin 8
76 #define LED_GREEN (1<<9) // pin 9
77 stlink_read_mem32(sl, GPIOC_CRH, 4);
78 uint32_t io_conf = read_uint32(sl->q_buf, 0);
79 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
81 // set: general purpose output push-pull, output mode, max speed 10 MHz.
82 write_uint32(sl->q_buf, 0x44444411);
83 stlink_write_mem32(sl, GPIOC_CRH, 4);
86 for (int i = 0; i < 100; i++) {
87 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
88 stlink_write_mem32(sl, GPIOC_ODR, 4);
89 /* stlink_read_mem32(sl, 0x4001100c, 4); */
90 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
94 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
97 write_uint32(sl->q_buf, io_conf); // set old state
101 // TODO rtfm: stlink doesn't have flash write routines
102 // writing to the flash area confuses the fw for the next read access
104 //stlink_read_mem32(sl, 0, 1024*6);
105 // flash 0x08000000 128kB
106 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
107 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
109 stlink_read_mem32(sl, 0x08000c00, 5);
110 stlink_read_mem32(sl, 0x08000c00, 4);
112 stlink_write_mem32(sl, 0x08000c00, 4);
113 stlink_read_mem32(sl, 0x08000c00, 256);
114 stlink_read_mem32(sl, 0x08000c00, 256);
117 // sram 0x20000000 8kB
118 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
120 stlink_write_mem8(sl, 0x20000000, 16);
123 stlink_write_mem8(sl, 0x20000000, 1);
124 stlink_write_mem8(sl, 0x20000001, 1);
125 stlink_write_mem8(sl, 0x2000000b, 3);
126 stlink_read_mem32(sl, 0x20000000, 16);
129 // a not aligned mem32 access doesn't work indeed
130 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
132 stlink_write_mem8(sl, 0x20000000, 32);
135 stlink_write_mem32(sl, 0x20000000, 1);
136 stlink_read_mem32(sl, 0x20000000, 16);
138 stlink_write_mem32(sl, 0x20000001, 1);
139 stlink_read_mem32(sl, 0x20000000, 16);
141 stlink_write_mem32(sl, 0x2000000b, 3);
142 stlink_read_mem32(sl, 0x20000000, 16);
145 stlink_write_mem32(sl, 0x20000000, 17);
146 stlink_read_mem32(sl, 0x20000000, 32);
149 // sram 0x20000000 8kB
150 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
152 stlink_write_mem8(sl, 0x20000000, 64);
153 stlink_read_mem32(sl, 0x20000000, 64);
156 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
157 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
158 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
161 stlink_read_all_regs(sl);
163 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
164 stlink_write_reg(sl, 0x12345678, 0);
165 stlink_read_reg(sl, 0);
166 stlink_read_all_regs(sl);
172 stlink_force_debug(sl);
175 #if 1 /* read the system bootloader */
176 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
177 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
179 #if 0 /* read the flash memory */
180 fputs("\n+++++++ read flash memory\n\n", stderr);
182 stlink_read_mem32(sl, 0x08000000, 4);
184 #if 0 /* flash programming */
185 fputs("\n+++++++ program flash memory\n\n", stderr);
186 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
188 #if 0 /* check file contents */
189 fputs("\n+++++++ check flash memory\n\n", stderr);
191 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
192 printf("_____ stlink_fcheck_flash() == %d\n", res);
196 fputs("\n+++++++ sram write and execute\n\n", stderr);
197 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
198 stlink_run_at(sl, sl->sram_base);
203 //----------------------------------------------------------------------
204 // back to mass mode, just in case ...
205 stlink_exit_debug_mode(sl);
206 stlink_current_mode(sl);
209 //fflush(stderr); fflush(stdout);