4 * main() ripped out of old stlink-hw.c
9 #include "stlink-common.h"
11 int main(int argc, char *argv[]) {
12 // set scpi lib debug level: 0 for no debug info, 10 for lots
18 "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
19 "\n*** Notice: The stlink firmware violates the USB standard.\n"
20 "*** If you plug-in the discovery's stlink, wait a several\n"
21 "*** minutes to let the kernel driver swallow the broken device.\n"
22 "*** Watch:\ntail -f /var/log/messages\n"
23 "*** This command sequence can shorten the waiting time and fix some issues.\n"
24 "*** Unplug the stlink and execute once as root:\n"
25 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
32 fprintf(stderr, "bzzt\n");
36 stlink_t *sl = stlink_v1_open(dev_name, 99);
40 // we are in mass mode, go to swd
41 stlink_enter_swd_mode(sl);
42 stlink_current_mode(sl);
44 //----------------------------------------------------------------------
47 //stlink_force_debug(sl);
51 // core system control block
52 stlink_read_mem32(sl, 0xe000ed00, 4);
53 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
55 stlink_read_mem32(sl, 0xe000ed90, 4);
56 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
58 stlink_read_mem32(sl, 0xe000edf0, 4);
59 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
61 stlink_read_mem32(sl, 0x4001100c, 4);
62 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
65 // happy new year 2011: let blink all the leds
66 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
68 #define GPIOC 0x40011000 // port C
69 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
70 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
71 #define LED_BLUE (1<<8) // pin 8
72 #define LED_GREEN (1<<9) // pin 9
73 stlink_read_mem32(sl, GPIOC_CRH, 4);
74 uint32_t io_conf = read_uint32(sl->q_buf, 0);
75 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
77 // set: general purpose output push-pull, output mode, max speed 10 MHz.
78 write_uint32(sl->q_buf, 0x44444411);
79 stlink_write_mem32(sl, GPIOC_CRH, 4);
82 for (int i = 0; i < 100; i++) {
83 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
84 stlink_write_mem32(sl, GPIOC_ODR, 4);
85 /* stlink_read_mem32(sl, 0x4001100c, 4); */
86 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
90 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
93 write_uint32(sl->q_buf, io_conf); // set old state
97 // TODO rtfm: stlink doesn't have flash write routines
98 // writing to the flash area confuses the fw for the next read access
100 //stlink_read_mem32(sl, 0, 1024*6);
101 // flash 0x08000000 128kB
102 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
103 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
105 stlink_read_mem32(sl, 0x08000c00, 5);
106 stlink_read_mem32(sl, 0x08000c00, 4);
108 stlink_write_mem32(sl, 0x08000c00, 4);
109 stlink_read_mem32(sl, 0x08000c00, 256);
110 stlink_read_mem32(sl, 0x08000c00, 256);
113 // sram 0x20000000 8kB
114 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
116 stlink_write_mem8(sl, 0x20000000, 16);
119 stlink_write_mem8(sl, 0x20000000, 1);
120 stlink_write_mem8(sl, 0x20000001, 1);
121 stlink_write_mem8(sl, 0x2000000b, 3);
122 stlink_read_mem32(sl, 0x20000000, 16);
125 // a not aligned mem32 access doesn't work indeed
126 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
128 stlink_write_mem8(sl, 0x20000000, 32);
131 stlink_write_mem32(sl, 0x20000000, 1);
132 stlink_read_mem32(sl, 0x20000000, 16);
134 stlink_write_mem32(sl, 0x20000001, 1);
135 stlink_read_mem32(sl, 0x20000000, 16);
137 stlink_write_mem32(sl, 0x2000000b, 3);
138 stlink_read_mem32(sl, 0x20000000, 16);
141 stlink_write_mem32(sl, 0x20000000, 17);
142 stlink_read_mem32(sl, 0x20000000, 32);
145 // sram 0x20000000 8kB
146 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
148 stlink_write_mem8(sl, 0x20000000, 64);
149 stlink_read_mem32(sl, 0x20000000, 64);
152 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
153 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
154 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
157 stlink_read_all_regs(sl);
159 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
160 stlink_write_reg(sl, 0x12345678, 0);
161 stlink_read_reg(sl, 0);
162 stlink_read_all_regs(sl);
168 stlink_force_debug(sl);
171 #if 0 /* read the system bootloader */
172 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
173 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
175 #if 0 /* read the flash memory */
176 fputs("\n+++++++ read flash memory\n\n", stderr);
178 stlink_read_mem32(sl, 0x08000000, 4);
180 #if 0 /* flash programming */
181 fputs("\n+++++++ program flash memory\n\n", stderr);
182 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
184 #if 0 /* check file contents */
185 fputs("\n+++++++ check flash memory\n\n", stderr);
187 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
188 printf("_____ stlink_fcheck_flash() == %d\n", res);
192 fputs("\n+++++++ sram write and execute\n\n", stderr);
193 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
194 stlink_run_at(sl, sl->sram_base);
200 //----------------------------------------------------------------------
201 // back to mass mode, just in case ...
202 stlink_exit_debug_mode(sl);
203 stlink_current_mode(sl);
207 //fflush(stderr); fflush(stdout);