4 * main() ripped out of old stlink-hw.c
10 #include "stlink-common.h"
11 #include "uglylogging.h"
13 #define LOG_TAG __FILE__
14 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
15 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
16 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
17 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
19 static void __attribute__((unused)) mark_buf(stlink_t *sl) {
20 memset(sl->q_buf, 0, sizeof(sl->q_buf));
30 sl->q_buf[1024 * 6 - 1] = 0x42; //6kB
31 sl->q_buf[1024 * 8 - 1] = 0x42; //8kB
35 int main(int argc, char *argv[]) {
36 // set scpi lib debug level: 0 for no debug info, 10 for lots
41 "\nUsage: stlink-access-test [anything at all] ...\n"
42 "\n*** Notice: The stlink firmware violates the USB standard.\n"
43 "*** Because we just use libusb, we can just tell the kernel's\n"
44 "*** driver to simply ignore the device...\n"
45 "*** Unplug the stlink and execute once as root:\n"
46 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n",
53 stlink_t *sl = stlink_v1_open(99);
57 // we are in mass mode, go to swd
58 stlink_enter_swd_mode(sl);
59 stlink_current_mode(sl);
61 //----------------------------------------------------------------------
64 //stlink_force_debug(sl);
67 // core system control block
68 stlink_read_mem32(sl, 0xe000ed00, 4);
69 DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0));
71 stlink_read_mem32(sl, 0xe000ed90, 4);
72 DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0));
75 stlink_read_mem32(sl, 0xe000edf0, 4);
76 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
78 stlink_read_mem32(sl, 0x4001100c, 4);
79 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
82 // happy new year 2011: let blink all the leds
83 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
85 #define GPIOC 0x40011000 // port C
86 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
87 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
88 #define LED_BLUE (1<<8) // pin 8
89 #define LED_GREEN (1<<9) // pin 9
90 stlink_read_mem32(sl, GPIOC_CRH, 4);
91 uint32_t io_conf = read_uint32(sl->q_buf, 0);
92 DLOG("GPIOC_CRH = 0x%08x\n", io_conf);
94 // set: general purpose output push-pull, output mode, max speed 10 MHz.
95 write_uint32(sl->q_buf, 0x44444411);
96 stlink_write_mem32(sl, GPIOC_CRH, 4);
98 memset(sl->q_buf, 0, sizeof(sl->q_buf));
99 for (int i = 0; i < 100; i++) {
100 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
101 stlink_write_mem32(sl, GPIOC_ODR, 4);
102 /* stlink_read_mem32(sl, 0x4001100c, 4); */
103 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
106 memset(sl->q_buf, 0, sizeof(sl->q_buf));
107 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
110 write_uint32(sl->q_buf, io_conf); // set old state
114 // TODO rtfm: stlink doesn't have flash write routines
115 // writing to the flash area confuses the fw for the next read access
117 //stlink_read_mem32(sl, 0, 1024*6);
118 // flash 0x08000000 128kB
119 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
120 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
122 stlink_read_mem32(sl, 0x08000c00, 5);
123 stlink_read_mem32(sl, 0x08000c00, 4);
125 stlink_write_mem32(sl, 0x08000c00, 4);
126 stlink_read_mem32(sl, 0x08000c00, 256);
127 stlink_read_mem32(sl, 0x08000c00, 256);
130 // sram 0x20000000 8kB
131 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
132 memset(sl->q_buf, 0, sizeof(sl->q_buf));
134 //stlink_write_mem8(sl, 0x20000000, 16);
136 //stlink_write_mem8(sl, 0x20000000, 1);
137 //stlink_write_mem8(sl, 0x20000001, 1);
138 stlink_write_mem8(sl, 0x2000000b, 3);
139 stlink_read_mem32(sl, 0x20000000, 16);
142 // a not aligned mem32 access doesn't work indeed
143 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
144 memset(sl->q_buf, 0, sizeof(sl->q_buf));
146 stlink_write_mem32(sl, 0x20000000, 1);
147 stlink_read_mem32(sl, 0x20000000, 16);
149 stlink_write_mem32(sl, 0x20000001, 1);
150 stlink_read_mem32(sl, 0x20000000, 16);
152 stlink_write_mem32(sl, 0x2000000b, 3);
153 stlink_read_mem32(sl, 0x20000000, 16);
156 stlink_write_mem32(sl, 0x20000000, 17);
157 stlink_read_mem32(sl, 0x20000000, 32);
160 // sram 0x20000000 8kB
161 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
162 memset(sl->q_buf, 0, sizeof(sl->q_buf));
164 stlink_write_mem8(sl, 0x20000000, 64);
165 stlink_read_mem32(sl, 0x20000000, 64);
168 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
169 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
170 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
174 stlink_read_all_regs(sl, ®s);
176 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
177 stlink_write_reg(sl, 0x12345678, 0);
178 stlink_read_reg(sl, 0, ®s);
179 stlink_read_all_regs(sl, ®s);
185 stlink_force_debug(sl);
188 #if 0 /* read the system bootloader */
189 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
190 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
192 #if 0 /* read the flash memory */
193 fputs("\n+++++++ read flash memory\n\n", stderr);
195 stlink_read_mem32(sl, 0x08000000, 4);
197 #if 0 /* flash programming */
198 fputs("\n+++++++ program flash memory\n\n", stderr);
199 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
201 #if 0 /* check file contents */
202 fputs("\n+++++++ check flash memory\n\n", stderr);
204 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
205 printf("_____ stlink_fcheck_flash() == %d\n", res);
209 fputs("\n+++++++ sram write and execute\n\n", stderr);
210 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
211 stlink_run_at(sl, sl->sram_base);
217 //----------------------------------------------------------------------
218 // back to mass mode, just in case ...
219 stlink_exit_debug_mode(sl);
220 stlink_current_mode(sl);
224 //fflush(stderr); fflush(stdout);