4 * main() ripped out of old stlink-hw.c
10 #include <scsi/sg_lib.h>
11 #include <scsi/sg_pt.h>
13 #include "stlink-common.h"
15 int main(int argc, char *argv[]) {
16 // set scpi lib debug level: 0 for no debug info, 10 for lots
17 const int scsi_verbose = 2;
23 "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
24 "\n*** Notice: The stlink firmware violates the USB standard.\n"
25 "*** If you plug-in the discovery's stlink, wait a several\n"
26 "*** minutes to let the kernel driver swallow the broken device.\n"
27 "*** Watch:\ntail -f /var/log/messages\n"
28 "*** This command sequence can shorten the waiting time and fix some issues.\n"
29 "*** Unplug the stlink and execute once as root:\n"
30 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
40 fputs("*** stlink access test ***\n", stderr);
41 fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(),
44 stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose);
48 // we are in mass mode, go to swd
49 stlink_enter_swd_mode(sl);
50 stlink_current_mode(sl);
52 //----------------------------------------------------------------------
55 //stlink_force_debug(sl);
59 // core system control block
60 stlink_read_mem32(sl, 0xe000ed00, 4);
61 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
63 stlink_read_mem32(sl, 0xe000ed90, 4);
64 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
66 stlink_read_mem32(sl, 0xe000edf0, 4);
67 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
69 stlink_read_mem32(sl, 0x4001100c, 4);
70 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
73 // happy new year 2011: let blink all the leds
74 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
76 #define GPIOC 0x40011000 // port C
77 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
78 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
79 #define LED_BLUE (1<<8) // pin 8
80 #define LED_GREEN (1<<9) // pin 9
81 stlink_read_mem32(sl, GPIOC_CRH, 4);
82 uint32_t io_conf = read_uint32(sl->q_buf, 0);
83 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
85 // set: general purpose output push-pull, output mode, max speed 10 MHz.
86 write_uint32(sl->q_buf, 0x44444411);
87 stlink_write_mem32(sl, GPIOC_CRH, 4);
90 for (int i = 0; i < 100; i++) {
91 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
92 stlink_write_mem32(sl, GPIOC_ODR, 4);
93 /* stlink_read_mem32(sl, 0x4001100c, 4); */
94 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
98 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
101 write_uint32(sl->q_buf, io_conf); // set old state
105 // TODO rtfm: stlink doesn't have flash write routines
106 // writing to the flash area confuses the fw for the next read access
108 //stlink_read_mem32(sl, 0, 1024*6);
109 // flash 0x08000000 128kB
110 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
111 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
113 stlink_read_mem32(sl, 0x08000c00, 5);
114 stlink_read_mem32(sl, 0x08000c00, 4);
116 stlink_write_mem32(sl, 0x08000c00, 4);
117 stlink_read_mem32(sl, 0x08000c00, 256);
118 stlink_read_mem32(sl, 0x08000c00, 256);
121 // sram 0x20000000 8kB
122 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
124 stlink_write_mem8(sl, 0x20000000, 16);
127 stlink_write_mem8(sl, 0x20000000, 1);
128 stlink_write_mem8(sl, 0x20000001, 1);
129 stlink_write_mem8(sl, 0x2000000b, 3);
130 stlink_read_mem32(sl, 0x20000000, 16);
133 // a not aligned mem32 access doesn't work indeed
134 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
136 stlink_write_mem8(sl, 0x20000000, 32);
139 stlink_write_mem32(sl, 0x20000000, 1);
140 stlink_read_mem32(sl, 0x20000000, 16);
142 stlink_write_mem32(sl, 0x20000001, 1);
143 stlink_read_mem32(sl, 0x20000000, 16);
145 stlink_write_mem32(sl, 0x2000000b, 3);
146 stlink_read_mem32(sl, 0x20000000, 16);
149 stlink_write_mem32(sl, 0x20000000, 17);
150 stlink_read_mem32(sl, 0x20000000, 32);
153 // sram 0x20000000 8kB
154 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
156 stlink_write_mem8(sl, 0x20000000, 64);
157 stlink_read_mem32(sl, 0x20000000, 64);
160 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
161 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
162 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
165 stlink_read_all_regs(sl);
167 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
168 stlink_write_reg(sl, 0x12345678, 0);
169 stlink_read_reg(sl, 0);
170 stlink_read_all_regs(sl);
176 stlink_force_debug(sl);
179 #if 1 /* read the system bootloader */
180 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
181 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
183 #if 0 /* read the flash memory */
184 fputs("\n+++++++ read flash memory\n\n", stderr);
186 stlink_read_mem32(sl, 0x08000000, 4);
188 #if 0 /* flash programming */
189 fputs("\n+++++++ program flash memory\n\n", stderr);
190 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
192 #if 0 /* check file contents */
193 fputs("\n+++++++ check flash memory\n\n", stderr);
195 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
196 printf("_____ stlink_fcheck_flash() == %d\n", res);
200 fputs("\n+++++++ sram write and execute\n\n", stderr);
201 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
202 stlink_run_at(sl, sl->sram_base);
207 //----------------------------------------------------------------------
208 // back to mass mode, just in case ...
209 stlink_exit_debug_mode(sl);
210 stlink_current_mode(sl);
213 //fflush(stderr); fflush(stdout);