4 * main() ripped out of old stlink-hw.c
9 #include <scsi/sg_lib.h>
10 #include <scsi/sg_pt.h>
11 #include "stlink-common.h"
13 int main(int argc, char *argv[]) {
14 // set scpi lib debug level: 0 for no debug info, 10 for lots
15 const int scsi_verbose = 2;
21 "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
22 "\n*** Notice: The stlink firmware violates the USB standard.\n"
23 "*** If you plug-in the discovery's stlink, wait a several\n"
24 "*** minutes to let the kernel driver swallow the broken device.\n"
25 "*** Watch:\ntail -f /var/log/messages\n"
26 "*** This command sequence can shorten the waiting time and fix some issues.\n"
27 "*** Unplug the stlink and execute once as root:\n"
28 "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
38 fputs("*** stlink access test ***\n", stderr);
39 fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(),
42 stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose);
46 // we are in mass mode, go to swd
47 stlink_enter_swd_mode(sl);
48 stlink_current_mode(sl);
50 //----------------------------------------------------------------------
53 //stlink_force_debug(sl);
57 // core system control block
58 stlink_read_mem32(sl, 0xe000ed00, 4);
59 DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
61 stlink_read_mem32(sl, 0xe000ed90, 4);
62 DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
64 stlink_read_mem32(sl, 0xe000edf0, 4);
65 DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
67 stlink_read_mem32(sl, 0x4001100c, 4);
68 DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
71 // happy new year 2011: let blink all the leds
72 // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
74 #define GPIOC 0x40011000 // port C
75 #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
76 #define GPIOC_ODR (GPIOC + 0x0c) // port output data register
77 #define LED_BLUE (1<<8) // pin 8
78 #define LED_GREEN (1<<9) // pin 9
79 stlink_read_mem32(sl, GPIOC_CRH, 4);
80 uint32_t io_conf = read_uint32(sl->q_buf, 0);
81 DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
83 // set: general purpose output push-pull, output mode, max speed 10 MHz.
84 write_uint32(sl->q_buf, 0x44444411);
85 stlink_write_mem32(sl, GPIOC_CRH, 4);
88 for (int i = 0; i < 100; i++) {
89 write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
90 stlink_write_mem32(sl, GPIOC_ODR, 4);
91 /* stlink_read_mem32(sl, 0x4001100c, 4); */
92 /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
96 stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
99 write_uint32(sl->q_buf, io_conf); // set old state
103 // TODO rtfm: stlink doesn't have flash write routines
104 // writing to the flash area confuses the fw for the next read access
106 //stlink_read_mem32(sl, 0, 1024*6);
107 // flash 0x08000000 128kB
108 fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
109 stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
111 stlink_read_mem32(sl, 0x08000c00, 5);
112 stlink_read_mem32(sl, 0x08000c00, 4);
114 stlink_write_mem32(sl, 0x08000c00, 4);
115 stlink_read_mem32(sl, 0x08000c00, 256);
116 stlink_read_mem32(sl, 0x08000c00, 256);
119 // sram 0x20000000 8kB
120 fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
122 stlink_write_mem8(sl, 0x20000000, 16);
125 stlink_write_mem8(sl, 0x20000000, 1);
126 stlink_write_mem8(sl, 0x20000001, 1);
127 stlink_write_mem8(sl, 0x2000000b, 3);
128 stlink_read_mem32(sl, 0x20000000, 16);
131 // a not aligned mem32 access doesn't work indeed
132 fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
134 stlink_write_mem8(sl, 0x20000000, 32);
137 stlink_write_mem32(sl, 0x20000000, 1);
138 stlink_read_mem32(sl, 0x20000000, 16);
140 stlink_write_mem32(sl, 0x20000001, 1);
141 stlink_read_mem32(sl, 0x20000000, 16);
143 stlink_write_mem32(sl, 0x2000000b, 3);
144 stlink_read_mem32(sl, 0x20000000, 16);
147 stlink_write_mem32(sl, 0x20000000, 17);
148 stlink_read_mem32(sl, 0x20000000, 32);
151 // sram 0x20000000 8kB
152 fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
154 stlink_write_mem8(sl, 0x20000000, 64);
155 stlink_read_mem32(sl, 0x20000000, 64);
158 stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
159 stlink_read_mem32(sl, 0x20000000, 1024 * 6);
160 stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
163 stlink_read_all_regs(sl);
165 fputs("++++++++++ write r0 = 0x12345678\n", stderr);
166 stlink_write_reg(sl, 0x12345678, 0);
167 stlink_read_reg(sl, 0);
168 stlink_read_all_regs(sl);
174 stlink_force_debug(sl);
177 #if 1 /* read the system bootloader */
178 fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
179 stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
181 #if 0 /* read the flash memory */
182 fputs("\n+++++++ read flash memory\n\n", stderr);
184 stlink_read_mem32(sl, 0x08000000, 4);
186 #if 0 /* flash programming */
187 fputs("\n+++++++ program flash memory\n\n", stderr);
188 stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
190 #if 0 /* check file contents */
191 fputs("\n+++++++ check flash memory\n\n", stderr);
193 const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
194 printf("_____ stlink_fcheck_flash() == %d\n", res);
198 fputs("\n+++++++ sram write and execute\n\n", stderr);
199 stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
200 stlink_run_at(sl, sl->sram_base);
205 //----------------------------------------------------------------------
206 // back to mass mode, just in case ...
207 stlink_exit_debug_mode(sl);
208 stlink_current_mode(sl);
211 //fflush(stderr); fflush(stdout);