2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define HAS_RADIO_RATE 1
24 #define HAS_TELEMETRY 0
29 #define BEEPER_CHANNEL 4
31 #define HAS_SERIAL_1 0
37 #define USE_INTERNAL_FLASH 0
38 #define IGNITE_ON_P0 0
39 #define PACKET_HAS_MASTER 0
40 #define PACKET_HAS_SLAVE 0
41 #define AO_DATA_RING 32
42 #define HAS_FIXED_PAD_BOX 1
44 #define LOG_ERASE_MARK 0x55
46 /* 8MHz High speed external crystal */
47 #define AO_HSE 8000000
49 /* PLLVCO = 96MHz (so that USB will work) */
51 #define AO_RCC_CFGR_PLLMUL (STM_RCC_CFGR_PLLMUL_12)
53 #define AO_CC1200_FOSC 40000000
55 /* SYSCLK = 32MHz (no need to go faster than CPU) */
57 #define AO_RCC_CFGR_PLLDIV (STM_RCC_CFGR_PLLDIV_3)
59 /* HCLK = 32MHz (CPU clock) */
60 #define AO_AHB_PRESCALER 1
61 #define AO_RCC_CFGR_HPRE_DIV STM_RCC_CFGR_HPRE_DIV_1
63 /* Run APB1 at 16MHz (HCLK/2) */
64 #define AO_APB1_PRESCALER 2
65 #define AO_RCC_CFGR_PPRE1_DIV STM_RCC_CFGR_PPRE2_DIV_2
67 /* Run APB2 at 16MHz (HCLK/2) */
68 #define AO_APB2_PRESCALER 2
69 #define AO_RCC_CFGR_PPRE2_DIV STM_RCC_CFGR_PPRE2_DIV_2
72 #define USE_EEPROM_CONFIG 1
73 #define USE_STORAGE_CONFIG 0
76 #define HAS_RADIO_RATE 1
77 #define HAS_TELEMETRY 0
81 #define SPI_1_PA5_PA6_PA7 0
82 #define SPI_1_PB3_PB4_PB5 0
83 #define SPI_1_PE13_PE14_PE15 0
85 #define HAS_SPI_2 1 /* CC1200 */
86 #define SPI_2_PB13_PB14_PB15 1
87 #define SPI_2_PD1_PD3_PD4 0
88 #define SPI_2_GPIO (&stm_gpiob)
92 #define SPI_2_OSPEEDR STM_OSPEEDR_10MHz
98 #define PACKET_HAS_SLAVE 0
99 #define PACKET_HAS_MASTER 0
101 #define FAST_TIMER_FREQ 10000 /* .1ms for debouncing */
107 #define M25_MAX_CHIPS 1
108 #define AO_M25_SPI_CS_PORT (&stm_gpioa)
109 #define AO_M25_SPI_CS_MASK (1 << 15)
110 #define AO_M25_SPI_BUS AO_SPI_2_PB13_PB14_PB15
113 * Radio is a cc1200 connected via SPI
116 #define AO_RADIO_CAL_DEFAULT 5695733
118 #define AO_FEC_DEBUG 0
119 #define AO_CC1200_SPI_CS_PORT (&stm_gpioa)
120 #define AO_CC1200_SPI_CS_PIN 7
121 #define AO_CC1200_SPI_BUS AO_SPI_2_PB13_PB14_PB15
122 #define AO_CC1200_SPI stm_spi2
123 #define AO_CC1200_SPI_SPEED AO_SPI_SPEED_FAST
125 #define AO_CC1200_INT_PORT (&stm_gpiob)
126 #define AO_CC1200_INT_PIN (11)
128 #define AO_CC1200_INT_GPIO 2
129 #define AO_CC1200_INT_GPIO_IOCFG CC1200_IOCFG2
131 #define LED_PORT_0 (&stm_gpioa)
132 #define LED_PORT_1 (&stm_gpiob)
134 #define LED_PORT_0_ENABLE STM_RCC_AHBENR_GPIOAEN
135 #define LED_PORT_1_ENABLE STM_RCC_AHBENR_GPIOBEN
137 /* Port A, pins 4-6 */
138 #define LED_PORT_0_SHIFT 4
139 #define LED_PORT_0_MASK 0x7
140 #define LED_PIN_GREEN 0
141 #define LED_PIN_AMBER 1
142 #define LED_PIN_RED 2
143 #define AO_LED_RED (1 << LED_PIN_RED)
144 #define AO_LED_AMBER (1 << LED_PIN_AMBER)
145 #define AO_LED_GREEN (1 << LED_PIN_GREEN)
147 /* Port B, pins 4-5 */
148 #define LED_PORT_1_SHIFT 0
149 #define LED_PORT_1_MASK (0x3 << 4)
150 #define LED_PIN_CONT_0 4
151 #define LED_PIN_ARMED 5
153 #define AO_LED_ARMED (1 << LED_PIN_ARMED)
154 #define AO_LED_CONTINUITY(c) (1 << (4 - (c)))
155 #define AO_LED_CONTINUITY_MASK (0x1 << 4)
157 #define LEDS_AVAILABLE (LED_PORT_0_MASK|LED_PORT_1_MASK)
161 #define AO_SIREN_PORT (&stm_gpiob)
162 #define AO_SIREN_PIN 8
166 #define AO_STROBE_PORT (&stm_gpiob)
167 #define AO_STROBE_PIN 9
169 #define SPI_CONST 0x00
172 #define AO_PAD_PORT (&stm_gpioa)
174 #define AO_PAD_PIN_0 1
175 #define AO_PAD_ADC_0 0
177 #define AO_PAD_ALL_PINS ((1 << AO_PAD_PIN_0))
178 #define AO_PAD_ALL_CHANNELS ((1 << 0))
180 /* test these values with real igniters */
181 #define AO_PAD_RELAY_CLOSED 3524
182 #define AO_PAD_NO_IGNITER 16904
183 #define AO_PAD_GOOD_IGNITER 22514
185 #define AO_PAD_ADC_PYRO 2
186 #define AO_PAD_ADC_BATT 8
188 #define AO_PAD_ADC_THRUST 3
189 #define AO_PAD_ADC_PRESSURE 18
191 #define AO_ADC_FIRST_PIN 0
195 #define AO_ADC_SQ1 AO_PAD_ADC_0
196 #define AO_ADC_SQ2 AO_PAD_ADC_PYRO
197 #define AO_ADC_SQ3 AO_PAD_ADC_BATT
198 #define AO_ADC_SQ4 AO_PAD_ADC_THRUST
199 #define AO_ADC_SQ5 AO_PAD_ADC_PRESSURE
201 #define AO_PYRO_R_PYRO_SENSE 200
202 #define AO_PYRO_R_SENSE_GND 22
204 #define AO_FIRE_R_POWER_FET 0
205 #define AO_FIRE_R_FET_SENSE 200
206 #define AO_FIRE_R_SENSE_GND 22
208 #define HAS_ADC_TEMP 0
211 int16_t sense[AO_PAD_NUM];
218 #define AO_ADC_DUMP(p) \
219 printf ("tick: %5u 0: %5d pyro: %5d batt %5d thrust %5d pressure %5d\n", \
227 #define AO_ADC_PINS ((1 << AO_PAD_ADC_0) | \
228 (1 << AO_PAD_ADC_PYRO) | \
229 (1 << AO_PAD_ADC_BATT) | \
230 (1 << AO_PAD_ADC_THRUST) | \
231 (1 << AO_PAD_ADC_PRESSURE))
233 #endif /* _AO_PINS_H_ */