1 # /* Peripheral and SRAM base address in the alias region */
\r
2 set PERIPH_BB_BASE 0x42000000
\r
3 set SRAM_BB_BASE 0x22000000
\r
5 # /*Peripheral and SRAM base address in the bit-band region */
\r
6 set SRAM_BASE 0x20000000
\r
7 set PERIPH_BASE 0x40000000
\r
9 # /*FSMC registers base address */
\r
10 set FSMC_R_BASE 0xA0000000
\r
12 # /*Peripheral memory map */
\r
13 set APB1PERIPH_BASE [set PERIPH_BASE]
\r
14 set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
\r
15 set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
\r
17 set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
\r
18 set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
\r
19 set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
\r
20 set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
\r
21 set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
\r
22 set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
\r
23 set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
\r
24 set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
\r
25 set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
\r
26 set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
\r
27 set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
\r
28 set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
\r
29 set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
\r
30 set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
\r
31 set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
\r
32 set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
\r
33 set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
\r
34 set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
\r
35 set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
\r
36 set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
\r
37 set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
\r
39 set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
\r
40 set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
\r
41 set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
\r
42 set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
\r
43 set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
\r
44 set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
\r
45 set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
\r
46 set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
\r
47 set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
\r
48 set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
\r
49 set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
\r
50 set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
\r
51 set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
\r
52 set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
\r
53 set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
\r
54 set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
\r
56 set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
\r
58 set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
\r
59 set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
\r
60 set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
\r
61 set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
\r
62 set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
\r
63 set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
\r
64 set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
\r
65 set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
\r
66 set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
\r
67 set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
\r
68 set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
\r
69 set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
\r
70 set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
\r
71 set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
\r
72 set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
\r
73 set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
\r
75 # /*Flash registers base address */
\r
76 set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
\r
77 # /*Flash Option Bytes base address */
\r
78 set OB_BASE 0x1FFFF800
\r
80 # /*FSMC Bankx registers base address */
\r
81 set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
\r
82 set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
\r
83 set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
\r
84 set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
\r
85 set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
\r
87 # /*Debug MCU registers base address */
\r
88 set DBGMCU_BASE 0xE0042000
\r
90 # /*System Control Space memory map */
\r
91 set SCS_BASE 0xE000E000
\r
93 set SysTick_BASE [expr $SCS_BASE + 0x0010]
\r
94 set NVIC_BASE [expr $SCS_BASE + 0x0100]
\r
95 set SCB_BASE [expr $SCS_BASE + 0x0D00]
\r