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   1 /***************************************************************************
   2  *   Copyright (C) 2006, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2009 Michael Schwingen                                  *
   9  *   michael@schwingen.org                                                 *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "breakpoints.h"
  31 #include "xscale.h"
  32 #include "target_type.h"
  33 #include "arm7_9_common.h"
  34 #include "arm_simulator.h"
  35 #include "arm_disassembler.h"
  36 #include "time_support.h"
  37 #include "image.h"
  38
  39
  40 /*
  41  * Important XScale documents available as of October 2009 include:
  42  *
  43  *  Intel XScale® Core Developer’s Manual, January 2004
  44  *              Order Number: 273473-002
  45  *      This has a chapter detailing debug facilities, and punts some
  46  *      details to chip-specific microarchitecture documents.
  47  *
  48  *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  49  *              Document Number: 273539-005
  50  *      Less detailed than the developer's manual, but summarizes those
  51  *      missing details (for most XScales) and gives LOTS of notes about
  52  *      debugger/handler interaction issues.  Presents a simpler reset
  53  *      and load-handler sequence than the arch doc.  (Note, OpenOCD
  54  *      doesn't currently support "Hot-Debug" as defined there.)
  55  *
  56  * Chip-specific microarchitecture documents may also be useful.
  57  */
  58
  59
  60 /* forward declarations */
  61 static int xscale_resume(struct target *, int current,
  62         uint32_t address, int handle_breakpoints, int debug_execution);
  63 static int xscale_debug_entry(struct target *);
  64 static int xscale_restore_context(struct target *);
  65 static int xscale_get_reg(struct reg *reg);
  66 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
  67 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
  68 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
  69 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
  70 static int xscale_read_trace(struct target *);
  71
  72
  73 /* This XScale "debug handler" is loaded into the processor's
  74  * mini-ICache, which is 2K of code writable only via JTAG.
  75  *
  76  * FIXME  the OpenOCD "bin2char" utility currently doesn't handle
  77  * binary files cleanly.  It's string oriented, and terminates them
  78  * with a NUL character.  Better would be to generate the constants
  79  * and let other code decide names, scoping, and other housekeeping.
  80  */
  81 static /* unsigned const char xscale_debug_handler[] = ... */
  82 #include "xscale_debug.h"
  83
  84 static char *const xscale_reg_list[] =
  85 {
  86         "XSCALE_MAINID",                /* 0 */
  87         "XSCALE_CACHETYPE",
  88         "XSCALE_CTRL",
  89         "XSCALE_AUXCTRL",
  90         "XSCALE_TTB",
  91         "XSCALE_DAC",
  92         "XSCALE_FSR",
  93         "XSCALE_FAR",
  94         "XSCALE_PID",
  95         "XSCALE_CPACCESS",
  96         "XSCALE_IBCR0",                 /* 10 */
  97         "XSCALE_IBCR1",
  98         "XSCALE_DBR0",
  99         "XSCALE_DBR1",
 100         "XSCALE_DBCON",
 101         "XSCALE_TBREG",
 102         "XSCALE_CHKPT0",
 103         "XSCALE_CHKPT1",
 104         "XSCALE_DCSR",
 105         "XSCALE_TX",
 106         "XSCALE_RX",                    /* 20 */
 107         "XSCALE_TXRXCTRL",
 108 };
 109
 110 static const struct xscale_reg xscale_reg_arch_info[] =
 111 {
 112         {XSCALE_MAINID, NULL},
 113         {XSCALE_CACHETYPE, NULL},
 114         {XSCALE_CTRL, NULL},
 115         {XSCALE_AUXCTRL, NULL},
 116         {XSCALE_TTB, NULL},
 117         {XSCALE_DAC, NULL},
 118         {XSCALE_FSR, NULL},
 119         {XSCALE_FAR, NULL},
 120         {XSCALE_PID, NULL},
 121         {XSCALE_CPACCESS, NULL},
 122         {XSCALE_IBCR0, NULL},
 123         {XSCALE_IBCR1, NULL},
 124         {XSCALE_DBR0, NULL},
 125         {XSCALE_DBR1, NULL},
 126         {XSCALE_DBCON, NULL},
 127         {XSCALE_TBREG, NULL},
 128         {XSCALE_CHKPT0, NULL},
 129         {XSCALE_CHKPT1, NULL},
 130         {XSCALE_DCSR, NULL}, /* DCSR accessed via JTAG or SW */
 131         {-1, NULL}, /* TX accessed via JTAG */
 132         {-1, NULL}, /* RX accessed via JTAG */
 133         {-1, NULL}, /* TXRXCTRL implicit access via JTAG */
 134 };
 135
 136 static int xscale_reg_arch_type = -1;
 137
 138 /* convenience wrapper to access XScale specific registers */
 139 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 140 {
 141         uint8_t buf[4];
 142
 143         buf_set_u32(buf, 0, 32, value);
 144
 145         return xscale_set_reg(reg, buf);
 146 }
 147
 148 static const char xscale_not[] = "target is not an XScale";
 149
 150 static int xscale_verify_pointer(struct command_context *cmd_ctx,
 151                 struct xscale_common *xscale)
 152 {
 153         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
 154                 command_print(cmd_ctx, xscale_not);
 155                 return ERROR_TARGET_INVALID;
 156         }
 157         return ERROR_OK;
 158 }
 159
 160 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
 161 {
 162         if (tap == NULL)
 163                 return ERROR_FAIL;
 164
 165         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 166         {
 167                 struct scan_field field;
 168                 uint8_t scratch[4];
 169
 170                 memset(&field, 0, sizeof field);
 171                 field.tap = tap;
 172                 field.num_bits = tap->ir_length;
 173                 field.out_value = scratch;
 174                 buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 175
 176                 jtag_add_ir_scan(1, &field, jtag_get_end_state());
 177         }
 178
 179         return ERROR_OK;
 180 }
 181
 182 static int xscale_read_dcsr(struct target *target)
 183 {
 184         struct xscale_common *xscale = target_to_xscale(target);
 185         int retval;
 186         struct scan_field fields[3];
 187         uint8_t field0 = 0x0;
 188         uint8_t field0_check_value = 0x2;
 189         uint8_t field0_check_mask = 0x7;
 190         uint8_t field2 = 0x0;
 191         uint8_t field2_check_value = 0x0;
 192         uint8_t field2_check_mask = 0x1;
 193
 194         jtag_set_end_state(TAP_DRPAUSE);
 195         xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
 196
 197         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 198         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 199
 200         memset(&fields, 0, sizeof fields);
 201
 202         fields[0].tap = target->tap;
 203         fields[0].num_bits = 3;
 204         fields[0].out_value = &field0;
 205         uint8_t tmp;
 206         fields[0].in_value = &tmp;
 207
 208         fields[1].tap = target->tap;
 209         fields[1].num_bits = 32;
 210         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 211
 212         fields[2].tap = target->tap;
 213         fields[2].num_bits = 1;
 214         fields[2].out_value = &field2;
 215         uint8_t tmp2;
 216         fields[2].in_value = &tmp2;
 217
 218         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 219
 220         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 221         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 222
 223         if ((retval = jtag_execute_queue()) != ERROR_OK)
 224         {
 225                 LOG_ERROR("JTAG error while reading DCSR");
 226                 return retval;
 227         }
 228
 229         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 230         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 231
 232         /* write the register with the value we just read
 233          * on this second pass, only the first bit of field0 is guaranteed to be 0)
 234          */
 235         field0_check_mask = 0x1;
 236         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 237         fields[1].in_value = NULL;
 238
 239         jtag_set_end_state(TAP_IDLE);
 240
 241         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 242
 243         /* DANGER!!! this must be here. It will make sure that the arguments
 244          * to jtag_set_check_value() does not go out of scope! */
 245         return jtag_execute_queue();
 246 }
 247
 248
 249 static void xscale_getbuf(jtag_callback_data_t arg)
 250 {
 251         uint8_t *in = (uint8_t *)arg;
 252         *((uint32_t *)in) = buf_get_u32(in, 0, 32);
 253 }
 254
 255 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
 256 {
 257         if (num_words == 0)
 258                 return ERROR_INVALID_ARGUMENTS;
 259
 260         int retval = ERROR_OK;
 261         tap_state_t path[3];
 262         struct scan_field fields[3];
 263         uint8_t *field0 = malloc(num_words * 1);
 264         uint8_t field0_check_value = 0x2;
 265         uint8_t field0_check_mask = 0x6;
 266         uint32_t *field1 = malloc(num_words * 4);
 267         uint8_t field2_check_value = 0x0;
 268         uint8_t field2_check_mask = 0x1;
 269         int words_done = 0;
 270         int words_scheduled = 0;
 271         int i;
 272
 273         path[0] = TAP_DRSELECT;
 274         path[1] = TAP_DRCAPTURE;
 275         path[2] = TAP_DRSHIFT;
 276
 277         memset(&fields, 0, sizeof fields);
 278
 279         fields[0].tap = target->tap;
 280         fields[0].num_bits = 3;
 281         fields[0].check_value = &field0_check_value;
 282         fields[0].check_mask = &field0_check_mask;
 283
 284         fields[1].tap = target->tap;
 285         fields[1].num_bits = 32;
 286
 287         fields[2].tap = target->tap;
 288         fields[2].num_bits = 1;
 289         fields[2].check_value = &field2_check_value;
 290         fields[2].check_mask = &field2_check_mask;
 291
 292         jtag_set_end_state(TAP_IDLE);
 293         xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
 294         jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 295
 296         /* repeat until all words have been collected */
 297         int attempts = 0;
 298         while (words_done < num_words)
 299         {
 300                 /* schedule reads */
 301                 words_scheduled = 0;
 302                 for (i = words_done; i < num_words; i++)
 303                 {
 304                         fields[0].in_value = &field0[i];
 305
 306                         jtag_add_pathmove(3, path);
 307
 308                         fields[1].in_value = (uint8_t *)(field1 + i);
 309
 310                         jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
 311
 312                         jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
 313
 314                         words_scheduled++;
 315                 }
 316
 317                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 318                 {
 319                         LOG_ERROR("JTAG error while receiving data from debug handler");
 320                         break;
 321                 }
 322
 323                 /* examine results */
 324                 for (i = words_done; i < num_words; i++)
 325                 {
 326                         if (!(field0[0] & 1))
 327                         {
 328                                 /* move backwards if necessary */
 329                                 int j;
 330                                 for (j = i; j < num_words - 1; j++)
 331                                 {
 332                                         field0[j] = field0[j + 1];
 333                                         field1[j] = field1[j + 1];
 334                                 }
 335                                 words_scheduled--;
 336                         }
 337                 }
 338                 if (words_scheduled == 0)
 339                 {
 340                         if (attempts++==1000)
 341                         {
 342                                 LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
 343                                 retval = ERROR_TARGET_TIMEOUT;
 344                                 break;
 345                         }
 346                 }
 347
 348                 words_done += words_scheduled;
 349         }
 350
 351         for (i = 0; i < num_words; i++)
 352                 *(buffer++) = buf_get_u32((uint8_t*)&field1[i], 0, 32);
 353
 354         free(field1);
 355
 356         return retval;
 357 }
 358
 359 static int xscale_read_tx(struct target *target, int consume)
 360 {
 361         struct xscale_common *xscale = target_to_xscale(target);
 362         tap_state_t path[3];
 363         tap_state_t noconsume_path[6];
 364         int retval;
 365         struct timeval timeout, now;
 366         struct scan_field fields[3];
 367         uint8_t field0_in = 0x0;
 368         uint8_t field0_check_value = 0x2;
 369         uint8_t field0_check_mask = 0x6;
 370         uint8_t field2_check_value = 0x0;
 371         uint8_t field2_check_mask = 0x1;
 372
 373         jtag_set_end_state(TAP_IDLE);
 374
 375         xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
 376
 377         path[0] = TAP_DRSELECT;
 378         path[1] = TAP_DRCAPTURE;
 379         path[2] = TAP_DRSHIFT;
 380
 381         noconsume_path[0] = TAP_DRSELECT;
 382         noconsume_path[1] = TAP_DRCAPTURE;
 383         noconsume_path[2] = TAP_DREXIT1;
 384         noconsume_path[3] = TAP_DRPAUSE;
 385         noconsume_path[4] = TAP_DREXIT2;
 386         noconsume_path[5] = TAP_DRSHIFT;
 387
 388         memset(&fields, 0, sizeof fields);
 389
 390         fields[0].tap = target->tap;
 391         fields[0].num_bits = 3;
 392         fields[0].in_value = &field0_in;
 393
 394         fields[1].tap = target->tap;
 395         fields[1].num_bits = 32;
 396         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 397
 398         fields[2].tap = target->tap;
 399         fields[2].num_bits = 1;
 400         uint8_t tmp;
 401         fields[2].in_value = &tmp;
 402
 403         gettimeofday(&timeout, NULL);
 404         timeval_add_time(&timeout, 1, 0);
 405
 406         for (;;)
 407         {
 408                 /* if we want to consume the register content (i.e. clear TX_READY),
 409                  * we have to go straight from Capture-DR to Shift-DR
 410                  * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
 411                 */
 412                 if (consume)
 413                         jtag_add_pathmove(3, path);
 414                 else
 415                 {
 416                         jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path);
 417                 }
 418
 419                 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
 420
 421                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 422                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 423
 424                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 425                 {
 426                         LOG_ERROR("JTAG error while reading TX");
 427                         return ERROR_TARGET_TIMEOUT;
 428                 }
 429
 430                 gettimeofday(&now, NULL);
 431                 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
 432                 {
 433                         LOG_ERROR("time out reading TX register");
 434                         return ERROR_TARGET_TIMEOUT;
 435                 }
 436                 if (!((!(field0_in & 1)) && consume))
 437                 {
 438                         goto done;
 439                 }
 440                 if (debug_level >= 3)
 441                 {
 442                         LOG_DEBUG("waiting 100ms");
 443                         alive_sleep(100); /* avoid flooding the logs */
 444                 } else
 445                 {
 446                         keep_alive();
 447                 }
 448         }
 449         done:
 450
 451         if (!(field0_in & 1))
 452                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 453
 454         return ERROR_OK;
 455 }
 456
 457 static int xscale_write_rx(struct target *target)
 458 {
 459         struct xscale_common *xscale = target_to_xscale(target);
 460         int retval;
 461         struct timeval timeout, now;
 462         struct scan_field fields[3];
 463         uint8_t field0_out = 0x0;
 464         uint8_t field0_in = 0x0;
 465         uint8_t field0_check_value = 0x2;
 466         uint8_t field0_check_mask = 0x6;
 467         uint8_t field2 = 0x0;
 468         uint8_t field2_check_value = 0x0;
 469         uint8_t field2_check_mask = 0x1;
 470
 471         jtag_set_end_state(TAP_IDLE);
 472
 473         xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
 474
 475         memset(&fields, 0, sizeof fields);
 476
 477         fields[0].tap = target->tap;
 478         fields[0].num_bits = 3;
 479         fields[0].out_value = &field0_out;
 480         fields[0].in_value = &field0_in;
 481
 482         fields[1].tap = target->tap;
 483         fields[1].num_bits = 32;
 484         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 485
 486         fields[2].tap = target->tap;
 487         fields[2].num_bits = 1;
 488         fields[2].out_value = &field2;
 489         uint8_t tmp;
 490         fields[2].in_value = &tmp;
 491
 492         gettimeofday(&timeout, NULL);
 493         timeval_add_time(&timeout, 1, 0);
 494
 495         /* poll until rx_read is low */
 496         LOG_DEBUG("polling RX");
 497         for (;;)
 498         {
 499                 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
 500
 501                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 502                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 503
 504                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 505                 {
 506                         LOG_ERROR("JTAG error while writing RX");
 507                         return retval;
 508                 }
 509
 510                 gettimeofday(&now, NULL);
 511                 if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
 512                 {
 513                         LOG_ERROR("time out writing RX register");
 514                         return ERROR_TARGET_TIMEOUT;
 515                 }
 516                 if (!(field0_in & 1))
 517                         goto done;
 518                 if (debug_level >= 3)
 519                 {
 520                         LOG_DEBUG("waiting 100ms");
 521                         alive_sleep(100); /* avoid flooding the logs */
 522                 } else
 523                 {
 524                         keep_alive();
 525                 }
 526         }
 527         done:
 528
 529         /* set rx_valid */
 530         field2 = 0x1;
 531         jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
 532
 533         if ((retval = jtag_execute_queue()) != ERROR_OK)
 534         {
 535                 LOG_ERROR("JTAG error while writing RX");
 536                 return retval;
 537         }
 538
 539         return ERROR_OK;
 540 }
 541
 542 /* send count elements of size byte to the debug handler */
 543 static int xscale_send(struct target *target, uint8_t *buffer, int count, int size)
 544 {
 545         uint32_t t[3];
 546         int bits[3];
 547         int retval;
 548         int done_count = 0;
 549
 550         jtag_set_end_state(TAP_IDLE);
 551
 552         xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
 553
 554         bits[0]=3;
 555         t[0]=0;
 556         bits[1]=32;
 557         t[2]=1;
 558         bits[2]=1;
 559         int endianness = target->endianness;
 560         while (done_count++ < count)
 561         {
 562                 switch (size)
 563                 {
 564                 case 4:
 565                         if (endianness == TARGET_LITTLE_ENDIAN)
 566                         {
 567                                 t[1]=le_to_h_u32(buffer);
 568                         } else
 569                         {
 570                                 t[1]=be_to_h_u32(buffer);
 571                         }
 572                         break;
 573                 case 2:
 574                         if (endianness == TARGET_LITTLE_ENDIAN)
 575                         {
 576                                 t[1]=le_to_h_u16(buffer);
 577                         } else
 578                         {
 579                                 t[1]=be_to_h_u16(buffer);
 580                         }
 581                         break;
 582                 case 1:
 583                         t[1]=buffer[0];
 584                         break;
 585                 default:
 586                         LOG_ERROR("BUG: size neither 4, 2 nor 1");
 587                         exit(-1);
 588                 }
 589                 jtag_add_dr_out(target->tap,
 590                                 3,
 591                                 bits,
 592                                 t,
 593                                 jtag_set_end_state(TAP_IDLE));
 594                 buffer += size;
 595         }
 596
 597         if ((retval = jtag_execute_queue()) != ERROR_OK)
 598         {
 599                 LOG_ERROR("JTAG error while sending data to debug handler");
 600                 return retval;
 601         }
 602
 603         return ERROR_OK;
 604 }
 605
 606 static int xscale_send_u32(struct target *target, uint32_t value)
 607 {
 608         struct xscale_common *xscale = target_to_xscale(target);
 609
 610         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
 611         return xscale_write_rx(target);
 612 }
 613
 614 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
 615 {
 616         struct xscale_common *xscale = target_to_xscale(target);
 617         int retval;
 618         struct scan_field fields[3];
 619         uint8_t field0 = 0x0;
 620         uint8_t field0_check_value = 0x2;
 621         uint8_t field0_check_mask = 0x7;
 622         uint8_t field2 = 0x0;
 623         uint8_t field2_check_value = 0x0;
 624         uint8_t field2_check_mask = 0x1;
 625
 626         if (hold_rst != -1)
 627                 xscale->hold_rst = hold_rst;
 628
 629         if (ext_dbg_brk != -1)
 630                 xscale->external_debug_break = ext_dbg_brk;
 631
 632         jtag_set_end_state(TAP_IDLE);
 633         xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
 634
 635         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 636         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 637
 638         memset(&fields, 0, sizeof fields);
 639
 640         fields[0].tap = target->tap;
 641         fields[0].num_bits = 3;
 642         fields[0].out_value = &field0;
 643         uint8_t tmp;
 644         fields[0].in_value = &tmp;
 645
 646         fields[1].tap = target->tap;
 647         fields[1].num_bits = 32;
 648         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 649
 650         fields[2].tap = target->tap;
 651         fields[2].num_bits = 1;
 652         fields[2].out_value = &field2;
 653         uint8_t tmp2;
 654         fields[2].in_value = &tmp2;
 655
 656         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 657
 658         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 659         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 660
 661         if ((retval = jtag_execute_queue()) != ERROR_OK)
 662         {
 663                 LOG_ERROR("JTAG error while writing DCSR");
 664                 return retval;
 665         }
 666
 667         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 668         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 669
 670         return ERROR_OK;
 671 }
 672
 673 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
 674 static unsigned int parity (unsigned int v)
 675 {
 676         // unsigned int ov = v;
 677         v ^= v >> 16;
 678         v ^= v >> 8;
 679         v ^= v >> 4;
 680         v &= 0xf;
 681         // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
 682         return (0x6996 >> v) & 1;
 683 }
 684
 685 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
 686 {
 687         uint8_t packet[4];
 688         uint8_t cmd;
 689         int word;
 690         struct scan_field fields[2];
 691
 692         LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 693
 694         /* LDIC into IR */
 695         jtag_set_end_state(TAP_IDLE);
 696         xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
 697
 698         /* CMD is b011 to load a cacheline into the Mini ICache.
 699          * Loading into the main ICache is deprecated, and unused.
 700          * It's followed by three zero bits, and 27 address bits.
 701          */
 702         buf_set_u32(&cmd, 0, 6, 0x3);
 703
 704         /* virtual address of desired cache line */
 705         buf_set_u32(packet, 0, 27, va >> 5);
 706
 707         memset(&fields, 0, sizeof fields);
 708
 709         fields[0].tap = target->tap;
 710         fields[0].num_bits = 6;
 711         fields[0].out_value = &cmd;
 712
 713         fields[1].tap = target->tap;
 714         fields[1].num_bits = 27;
 715         fields[1].out_value = packet;
 716
 717         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 718
 719         /* rest of packet is a cacheline: 8 instructions, with parity */
 720         fields[0].num_bits = 32;
 721         fields[0].out_value = packet;
 722
 723         fields[1].num_bits = 1;
 724         fields[1].out_value = &cmd;
 725
 726         for (word = 0; word < 8; word++)
 727         {
 728                 buf_set_u32(packet, 0, 32, buffer[word]);
 729
 730                 uint32_t value;
 731                 memcpy(&value, packet, sizeof(uint32_t));
 732                 cmd = parity(value);
 733
 734                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 735         }
 736
 737         return jtag_execute_queue();
 738 }
 739
 740 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 741 {
 742         uint8_t packet[4];
 743         uint8_t cmd;
 744         struct scan_field fields[2];
 745
 746         jtag_set_end_state(TAP_IDLE);
 747         xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
 748
 749         /* CMD for invalidate IC line b000, bits [6:4] b000 */
 750         buf_set_u32(&cmd, 0, 6, 0x0);
 751
 752         /* virtual address of desired cache line */
 753         buf_set_u32(packet, 0, 27, va >> 5);
 754
 755         memset(&fields, 0, sizeof fields);
 756
 757         fields[0].tap = target->tap;
 758         fields[0].num_bits = 6;
 759         fields[0].out_value = &cmd;
 760
 761         fields[1].tap = target->tap;
 762         fields[1].num_bits = 27;
 763         fields[1].out_value = packet;
 764
 765         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 766
 767         return ERROR_OK;
 768 }
 769
 770 static int xscale_update_vectors(struct target *target)
 771 {
 772         struct xscale_common *xscale = target_to_xscale(target);
 773         int i;
 774         int retval;
 775
 776         uint32_t low_reset_branch, high_reset_branch;
 777
 778         for (i = 1; i < 8; i++)
 779         {
 780                 /* if there's a static vector specified for this exception, override */
 781                 if (xscale->static_high_vectors_set & (1 << i))
 782                 {
 783                         xscale->high_vectors[i] = xscale->static_high_vectors[i];
 784                 }
 785                 else
 786                 {
 787                         retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
 788                         if (retval == ERROR_TARGET_TIMEOUT)
 789                                 return retval;
 790                         if (retval != ERROR_OK)
 791                         {
 792                                 /* Some of these reads will fail as part of normal execution */
 793                                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 794                         }
 795                 }
 796         }
 797
 798         for (i = 1; i < 8; i++)
 799         {
 800                 if (xscale->static_low_vectors_set & (1 << i))
 801                 {
 802                         xscale->low_vectors[i] = xscale->static_low_vectors[i];
 803                 }
 804                 else
 805                 {
 806                         retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
 807                         if (retval == ERROR_TARGET_TIMEOUT)
 808                                 return retval;
 809                         if (retval != ERROR_OK)
 810                         {
 811                                 /* Some of these reads will fail as part of normal execution */
 812                                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 813                         }
 814                 }
 815         }
 816
 817         /* calculate branches to debug handler */
 818         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
 819         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
 820
 821         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
 822         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
 823
 824         /* invalidate and load exception vectors in mini i-cache */
 825         xscale_invalidate_ic_line(target, 0x0);
 826         xscale_invalidate_ic_line(target, 0xffff0000);
 827
 828         xscale_load_ic(target, 0x0, xscale->low_vectors);
 829         xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 830
 831         return ERROR_OK;
 832 }
 833
 834 static int xscale_arch_state(struct target *target)
 835 {
 836         struct xscale_common *xscale = target_to_xscale(target);
 837         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
 838
 839         static const char *state[] =
 840         {
 841                 "disabled", "enabled"
 842         };
 843
 844         static const char *arch_dbg_reason[] =
 845         {
 846                 "", "\n(processor reset)", "\n(trace buffer full)"
 847         };
 848
 849         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 850         {
 851                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 852                 exit(-1);
 853         }
 854
 855         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 856                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 857                         "MMU: %s, D-Cache: %s, I-Cache: %s"
 858                         "%s",
 859                          armv4_5_state_strings[armv4_5->core_state],
 860                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 861                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 862                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 863                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 864                          state[xscale->armv4_5_mmu.mmu_enabled],
 865                          state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 866                          state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
 867                          arch_dbg_reason[xscale->arch_debug_reason]);
 868
 869         return ERROR_OK;
 870 }
 871
 872 static int xscale_poll(struct target *target)
 873 {
 874         int retval = ERROR_OK;
 875
 876         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
 877         {
 878                 enum target_state previous_state = target->state;
 879                 if ((retval = xscale_read_tx(target, 0)) == ERROR_OK)
 880                 {
 881
 882                         /* there's data to read from the tx register, we entered debug state */
 883                         target->state = TARGET_HALTED;
 884
 885                         /* process debug entry, fetching current mode regs */
 886                         retval = xscale_debug_entry(target);
 887                 }
 888                 else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 889                 {
 890                         LOG_USER("error while polling TX register, reset CPU");
 891                         /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
 892                         target->state = TARGET_HALTED;
 893                 }
 894
 895                 /* debug_entry could have overwritten target state (i.e. immediate resume)
 896                  * don't signal event handlers in that case
 897                  */
 898                 if (target->state != TARGET_HALTED)
 899                         return ERROR_OK;
 900
 901                 /* if target was running, signal that we halted
 902                  * otherwise we reentered from debug execution */
 903                 if (previous_state == TARGET_RUNNING)
 904                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 905                 else
 906                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 907         }
 908
 909         return retval;
 910 }
 911
 912 static int xscale_debug_entry(struct target *target)
 913 {
 914         struct xscale_common *xscale = target_to_xscale(target);
 915         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
 916         uint32_t pc;
 917         uint32_t buffer[10];
 918         int i;
 919         int retval;
 920         uint32_t moe;
 921
 922         /* clear external dbg break (will be written on next DCSR read) */
 923         xscale->external_debug_break = 0;
 924         if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
 925                 return retval;
 926
 927         /* get r0, pc, r1 to r7 and cpsr */
 928         if ((retval = xscale_receive(target, buffer, 10)) != ERROR_OK)
 929                 return retval;
 930
 931         /* move r0 from buffer to register cache */
 932         buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
 933         armv4_5->core_cache->reg_list[0].dirty = 1;
 934         armv4_5->core_cache->reg_list[0].valid = 1;
 935         LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 936
 937         /* move pc from buffer to register cache */
 938         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
 939         armv4_5->core_cache->reg_list[15].dirty = 1;
 940         armv4_5->core_cache->reg_list[15].valid = 1;
 941         LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 942
 943         /* move data from buffer to register cache */
 944         for (i = 1; i <= 7; i++)
 945         {
 946                 buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
 947                 armv4_5->core_cache->reg_list[i].dirty = 1;
 948                 armv4_5->core_cache->reg_list[i].valid = 1;
 949                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 950         }
 951
 952         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
 953         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 954         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 955         LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 956
 957         armv4_5->core_mode = buffer[9] & 0x1f;
 958         if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
 959         {
 960                 target->state = TARGET_UNKNOWN;
 961                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
 962                 return ERROR_TARGET_FAILURE;
 963         }
 964         LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
 965
 966         if (buffer[9] & 0x20)
 967                 armv4_5->core_state = ARMV4_5_STATE_THUMB;
 968         else
 969                 armv4_5->core_state = ARMV4_5_STATE_ARM;
 970
 971
 972         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 973                 return ERROR_FAIL;
 974
 975         /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
 976         if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
 977         {
 978                 xscale_receive(target, buffer, 8);
 979                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
 980                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
 981                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
 982         }
 983         else
 984         {
 985                 /* r8 to r14, but no spsr */
 986                 xscale_receive(target, buffer, 7);
 987         }
 988
 989         /* move data from buffer to register cache */
 990         for (i = 8; i <= 14; i++)
 991         {
 992                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, buffer[i - 8]);
 993                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 994                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 995         }
 996
 997         /* examine debug reason */
 998         xscale_read_dcsr(target);
 999         moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
1000
1001         /* stored PC (for calculating fixup) */
1002         pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1003
1004         switch (moe)
1005         {
1006                 case 0x0: /* Processor reset */
1007                         target->debug_reason = DBG_REASON_DBGRQ;
1008                         xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
1009                         pc -= 4;
1010                         break;
1011                 case 0x1: /* Instruction breakpoint hit */
1012                         target->debug_reason = DBG_REASON_BREAKPOINT;
1013                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1014                         pc -= 4;
1015                         break;
1016                 case 0x2: /* Data breakpoint hit */
1017                         target->debug_reason = DBG_REASON_WATCHPOINT;
1018                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1019                         pc -= 4;
1020                         break;
1021                 case 0x3: /* BKPT instruction executed */
1022                         target->debug_reason = DBG_REASON_BREAKPOINT;
1023                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1024                         pc -= 4;
1025                         break;
1026                 case 0x4: /* Ext. debug event */
1027                         target->debug_reason = DBG_REASON_DBGRQ;
1028                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1029                         pc -= 4;
1030                         break;
1031                 case 0x5: /* Vector trap occured */
1032                         target->debug_reason = DBG_REASON_BREAKPOINT;
1033                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
1034                         pc -= 4;
1035                         break;
1036                 case 0x6: /* Trace buffer full break */
1037                         target->debug_reason = DBG_REASON_DBGRQ;
1038                         xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
1039                         pc -= 4;
1040                         break;
1041                 case 0x7: /* Reserved (may flag Hot-Debug support) */
1042                 default:
1043                         LOG_ERROR("Method of Entry is 'Reserved'");
1044                         exit(-1);
1045                         break;
1046         }
1047
1048         /* apply PC fixup */
1049         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
1050
1051         /* on the first debug entry, identify cache type */
1052         if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1)
1053         {
1054                 uint32_t cache_type_reg;
1055
1056                 /* read cp15 cache type register */
1057                 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
1058                 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value, 0, 32);
1059
1060                 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
1061         }
1062
1063         /* examine MMU and Cache settings */
1064         /* read cp15 control register */
1065         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1066         xscale->cp15_control_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1067         xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1068         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1069         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1070
1071         /* tracing enabled, read collected trace data */
1072         if (xscale->trace.buffer_enabled)
1073         {
1074                 xscale_read_trace(target);
1075                 xscale->trace.buffer_fill--;
1076
1077                 /* resume if we're still collecting trace data */
1078                 if ((xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL)
1079                         && (xscale->trace.buffer_fill > 0))
1080                 {
1081                         xscale_resume(target, 1, 0x0, 1, 0);
1082                 }
1083                 else
1084                 {
1085                         xscale->trace.buffer_enabled = 0;
1086                 }
1087         }
1088
1089         return ERROR_OK;
1090 }
1091
1092 static int xscale_halt(struct target *target)
1093 {
1094         struct xscale_common *xscale = target_to_xscale(target);
1095
1096         LOG_DEBUG("target->state: %s",
1097                   target_state_name(target));
1098
1099         if (target->state == TARGET_HALTED)
1100         {
1101                 LOG_DEBUG("target was already halted");
1102                 return ERROR_OK;
1103         }
1104         else if (target->state == TARGET_UNKNOWN)
1105         {
1106                 /* this must not happen for a xscale target */
1107                 LOG_ERROR("target was in unknown state when halt was requested");
1108                 return ERROR_TARGET_INVALID;
1109         }
1110         else if (target->state == TARGET_RESET)
1111         {
1112                 LOG_DEBUG("target->state == TARGET_RESET");
1113         }
1114         else
1115         {
1116                 /* assert external dbg break */
1117                 xscale->external_debug_break = 1;
1118                 xscale_read_dcsr(target);
1119
1120                 target->debug_reason = DBG_REASON_DBGRQ;
1121         }
1122
1123         return ERROR_OK;
1124 }
1125
1126 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1127 {
1128         struct xscale_common *xscale = target_to_xscale(target);
1129         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1130         int retval;
1131
1132         if (xscale->ibcr0_used)
1133         {
1134                 struct breakpoint *ibcr0_bp = breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1135
1136                 if (ibcr0_bp)
1137                 {
1138                         xscale_unset_breakpoint(target, ibcr0_bp);
1139                 }
1140                 else
1141                 {
1142                         LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1143                         exit(-1);
1144                 }
1145         }
1146
1147         if ((retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1)) != ERROR_OK)
1148                 return retval;
1149
1150         return ERROR_OK;
1151 }
1152
1153 static int xscale_disable_single_step(struct target *target)
1154 {
1155         struct xscale_common *xscale = target_to_xscale(target);
1156         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1157         int retval;
1158
1159         if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
1160                 return retval;
1161
1162         return ERROR_OK;
1163 }
1164
1165 static void xscale_enable_watchpoints(struct target *target)
1166 {
1167         struct watchpoint *watchpoint = target->watchpoints;
1168
1169         while (watchpoint)
1170         {
1171                 if (watchpoint->set == 0)
1172                         xscale_set_watchpoint(target, watchpoint);
1173                 watchpoint = watchpoint->next;
1174         }
1175 }
1176
1177 static void xscale_enable_breakpoints(struct target *target)
1178 {
1179         struct breakpoint *breakpoint = target->breakpoints;
1180
1181         /* set any pending breakpoints */
1182         while (breakpoint)
1183         {
1184                 if (breakpoint->set == 0)
1185                         xscale_set_breakpoint(target, breakpoint);
1186                 breakpoint = breakpoint->next;
1187         }
1188 }
1189
1190 static int xscale_resume(struct target *target, int current,
1191                 uint32_t address, int handle_breakpoints, int debug_execution)
1192 {
1193         struct xscale_common *xscale = target_to_xscale(target);
1194         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
1195         struct breakpoint *breakpoint = target->breakpoints;
1196         uint32_t current_pc;
1197         int retval;
1198         int i;
1199
1200         LOG_DEBUG("-");
1201
1202         if (target->state != TARGET_HALTED)
1203         {
1204                 LOG_WARNING("target not halted");
1205                 return ERROR_TARGET_NOT_HALTED;
1206         }
1207
1208         if (!debug_execution)
1209         {
1210                 target_free_all_working_areas(target);
1211         }
1212
1213         /* update vector tables */
1214         if ((retval = xscale_update_vectors(target)) != ERROR_OK)
1215                 return retval;
1216
1217         /* current = 1: continue on current pc, otherwise continue at <address> */
1218         if (!current)
1219                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1220
1221         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1222
1223         /* if we're at the reset vector, we have to simulate the branch */
1224         if (current_pc == 0x0)
1225         {
1226                 arm_simulate_step(target, NULL);
1227                 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1228         }
1229
1230         /* the front-end may request us not to handle breakpoints */
1231         if (handle_breakpoints)
1232         {
1233                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1234                 {
1235                         uint32_t next_pc;
1236
1237                         /* there's a breakpoint at the current PC, we have to step over it */
1238                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1239                         xscale_unset_breakpoint(target, breakpoint);
1240
1241                         /* calculate PC of next instruction */
1242                         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1243                         {
1244                                 uint32_t current_opcode;
1245                                 target_read_u32(target, current_pc, &current_opcode);
1246                                 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1247                         }
1248
1249                         LOG_DEBUG("enable single-step");
1250                         xscale_enable_single_step(target, next_pc);
1251
1252                         /* restore banked registers */
1253                         xscale_restore_context(target);
1254
1255                         /* send resume request (command 0x30 or 0x31)
1256                          * clean the trace buffer if it is to be enabled (0x62) */
1257                         if (xscale->trace.buffer_enabled)
1258                         {
1259                                 xscale_send_u32(target, 0x62);
1260                                 xscale_send_u32(target, 0x31);
1261                         }
1262                         else
1263                                 xscale_send_u32(target, 0x30);
1264
1265                         /* send CPSR */
1266                         xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1267                         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1268
1269                         for (i = 7; i >= 0; i--)
1270                         {
1271                                 /* send register */
1272                                 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1273                                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1274                         }
1275
1276                         /* send PC */
1277                         xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1278                         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1279
1280                         /* wait for and process debug entry */
1281                         xscale_debug_entry(target);
1282
1283                         LOG_DEBUG("disable single-step");
1284                         xscale_disable_single_step(target);
1285
1286                         LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1287                         xscale_set_breakpoint(target, breakpoint);
1288                 }
1289         }
1290
1291         /* enable any pending breakpoints and watchpoints */
1292         xscale_enable_breakpoints(target);
1293         xscale_enable_watchpoints(target);
1294
1295         /* restore banked registers */
1296         xscale_restore_context(target);
1297
1298         /* send resume request (command 0x30 or 0x31)
1299          * clean the trace buffer if it is to be enabled (0x62) */
1300         if (xscale->trace.buffer_enabled)
1301         {
1302                 xscale_send_u32(target, 0x62);
1303                 xscale_send_u32(target, 0x31);
1304         }
1305         else
1306                 xscale_send_u32(target, 0x30);
1307
1308         /* send CPSR */
1309         xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1310         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1311
1312         for (i = 7; i >= 0; i--)
1313         {
1314                 /* send register */
1315                 xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1316                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1317         }
1318
1319         /* send PC */
1320         xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1321         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1322
1323         target->debug_reason = DBG_REASON_NOTHALTED;
1324
1325         if (!debug_execution)
1326         {
1327                 /* registers are now invalid */
1328                 armv4_5_invalidate_core_regs(target);
1329                 target->state = TARGET_RUNNING;
1330                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1331         }
1332         else
1333         {
1334                 target->state = TARGET_DEBUG_RUNNING;
1335                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1336         }
1337
1338         LOG_DEBUG("target resumed");
1339
1340         return ERROR_OK;
1341 }
1342
1343 static int xscale_step_inner(struct target *target, int current,
1344                 uint32_t address, int handle_breakpoints)
1345 {
1346         struct xscale_common *xscale = target_to_xscale(target);
1347         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
1348         uint32_t next_pc;
1349         int retval;
1350         int i;
1351
1352         target->debug_reason = DBG_REASON_SINGLESTEP;
1353
1354         /* calculate PC of next instruction */
1355         if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1356         {
1357                 uint32_t current_opcode, current_pc;
1358                 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1359
1360                 target_read_u32(target, current_pc, &current_opcode);
1361                 LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1362                 return retval;
1363         }
1364
1365         LOG_DEBUG("enable single-step");
1366         if ((retval = xscale_enable_single_step(target, next_pc)) != ERROR_OK)
1367                 return retval;
1368
1369         /* restore banked registers */
1370         if ((retval = xscale_restore_context(target)) != ERROR_OK)
1371                 return retval;
1372
1373         /* send resume request (command 0x30 or 0x31)
1374          * clean the trace buffer if it is to be enabled (0x62) */
1375         if (xscale->trace.buffer_enabled)
1376         {
1377                 if ((retval = xscale_send_u32(target, 0x62)) != ERROR_OK)
1378                         return retval;
1379                 if ((retval = xscale_send_u32(target, 0x31)) != ERROR_OK)
1380                         return retval;
1381         }
1382         else
1383                 if ((retval = xscale_send_u32(target, 0x30)) != ERROR_OK)
1384                         return retval;
1385
1386         /* send CPSR */
1387         if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32))) != ERROR_OK)
1388                 return retval;
1389         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1390
1391         for (i = 7; i >= 0; i--)
1392         {
1393                 /* send register */
1394                 if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK)
1395                         return retval;
1396                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
1397         }
1398
1399         /* send PC */
1400         if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))) != ERROR_OK)
1401                 return retval;
1402         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1403
1404         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1405
1406         /* registers are now invalid */
1407         if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
1408                 return retval;
1409
1410         /* wait for and process debug entry */
1411         if ((retval = xscale_debug_entry(target)) != ERROR_OK)
1412                 return retval;
1413
1414         LOG_DEBUG("disable single-step");
1415         if ((retval = xscale_disable_single_step(target)) != ERROR_OK)
1416                 return retval;
1417
1418         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1419
1420         return ERROR_OK;
1421 }
1422
1423 static int xscale_step(struct target *target, int current,
1424                 uint32_t address, int handle_breakpoints)
1425 {
1426         struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
1427         struct breakpoint *breakpoint = target->breakpoints;
1428
1429         uint32_t current_pc;
1430         int retval;
1431
1432         if (target->state != TARGET_HALTED)
1433         {
1434                 LOG_WARNING("target not halted");
1435                 return ERROR_TARGET_NOT_HALTED;
1436         }
1437
1438         /* current = 1: continue on current pc, otherwise continue at <address> */
1439         if (!current)
1440                 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1441
1442         current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1443
1444         /* if we're at the reset vector, we have to simulate the step */
1445         if (current_pc == 0x0)
1446         {
1447                 if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK)
1448                         return retval;
1449                 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1450
1451                 target->debug_reason = DBG_REASON_SINGLESTEP;
1452                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1453
1454                 return ERROR_OK;
1455         }
1456
1457         /* the front-end may request us not to handle breakpoints */
1458         if (handle_breakpoints)
1459                 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1460                 {
1461                         if ((retval = xscale_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1462                                 return retval;
1463                 }
1464
1465         retval = xscale_step_inner(target, current, address, handle_breakpoints);
1466
1467         if (breakpoint)
1468         {
1469                 xscale_set_breakpoint(target, breakpoint);
1470         }
1471
1472         LOG_DEBUG("target stepped");
1473
1474         return ERROR_OK;
1475
1476 }
1477
1478 static int xscale_assert_reset(struct target *target)
1479 {
1480         struct xscale_common *xscale = target_to_xscale(target);
1481
1482         LOG_DEBUG("target->state: %s",
1483                   target_state_name(target));
1484
1485         /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1486          * end up in T-L-R, which would reset JTAG
1487          */
1488         jtag_set_end_state(TAP_IDLE);
1489         xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
1490
1491         /* set Hold reset, Halt mode and Trap Reset */
1492         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1493         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1494         xscale_write_dcsr(target, 1, 0);
1495
1496         /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1497         xscale_jtag_set_instr(target->tap, 0x7f);
1498         jtag_execute_queue();
1499
1500         /* assert reset */
1501         jtag_add_reset(0, 1);
1502
1503         /* sleep 1ms, to be sure we fulfill any requirements */
1504         jtag_add_sleep(1000);
1505         jtag_execute_queue();
1506
1507         target->state = TARGET_RESET;
1508
1509     if (target->reset_halt)
1510     {
1511         int retval;
1512                 if ((retval = target_halt(target)) != ERROR_OK)
1513                         return retval;
1514     }
1515
1516         return ERROR_OK;
1517 }
1518
1519 static int xscale_deassert_reset(struct target *target)
1520 {
1521         struct xscale_common *xscale = target_to_xscale(target);
1522         struct breakpoint *breakpoint = target->breakpoints;
1523
1524         LOG_DEBUG("-");
1525
1526         xscale->ibcr_available = 2;
1527         xscale->ibcr0_used = 0;
1528         xscale->ibcr1_used = 0;
1529
1530         xscale->dbr_available = 2;
1531         xscale->dbr0_used = 0;
1532         xscale->dbr1_used = 0;
1533
1534         /* mark all hardware breakpoints as unset */
1535         while (breakpoint)
1536         {
1537                 if (breakpoint->type == BKPT_HARD)
1538                 {
1539                         breakpoint->set = 0;
1540                 }
1541                 breakpoint = breakpoint->next;
1542         }
1543
1544         armv4_5_invalidate_core_regs(target);
1545
1546         /* FIXME mark hardware watchpoints got unset too.  Also,
1547          * at least some of the XScale registers are invalid...
1548          */
1549
1550         /*
1551          * REVISIT:  *assumes* we had a SRST+TRST reset so the mini-icache
1552          * contents got invalidated.  Safer to force that, so writing new
1553          * contents can't ever fail..
1554          */
1555         {
1556                 uint32_t address;
1557                 unsigned buf_cnt;
1558                 const uint8_t *buffer = xscale_debug_handler;
1559                 int retval;
1560
1561                 /* release SRST */
1562                 jtag_add_reset(0, 0);
1563
1564                 /* wait 300ms; 150 and 100ms were not enough */
1565                 jtag_add_sleep(300*1000);
1566
1567                 jtag_add_runtest(2030, jtag_set_end_state(TAP_IDLE));
1568                 jtag_execute_queue();
1569
1570                 /* set Hold reset, Halt mode and Trap Reset */
1571                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1572                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1573                 xscale_write_dcsr(target, 1, 0);
1574
1575                 /* Load the debug handler into the mini-icache.  Since
1576                  * it's using halt mode (not monitor mode), it runs in
1577                  * "Special Debug State" for access to registers, memory,
1578                  * coprocessors, trace data, etc.
1579                  */
1580                 address = xscale->handler_address;
1581                 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1582                                 binary_size > 0;
1583                                 binary_size -= buf_cnt, buffer += buf_cnt)
1584                 {
1585                         uint32_t cache_line[8];
1586                         unsigned i;
1587
1588                         buf_cnt = binary_size;
1589                         if (buf_cnt > 32)
1590                                 buf_cnt = 32;
1591
1592                         for (i = 0; i < buf_cnt; i += 4)
1593                         {
1594                                 /* convert LE buffer to host-endian uint32_t */
1595                                 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1596                         }
1597
1598                         for (; i < 32; i += 4)
1599                         {
1600                                 cache_line[i / 4] = 0xe1a08008;
1601                         }
1602
1603                         /* only load addresses other than the reset vectors */
1604                         if ((address % 0x400) != 0x0)
1605                         {
1606                                 retval = xscale_load_ic(target, address,
1607                                                 cache_line);
1608                                 if (retval != ERROR_OK)
1609                                         return retval;
1610                         }
1611
1612                         address += buf_cnt;
1613                 };
1614
1615                 retval = xscale_load_ic(target, 0x0,
1616                                         xscale->low_vectors);
1617                 if (retval != ERROR_OK)
1618                         return retval;
1619                 retval = xscale_load_ic(target, 0xffff0000,
1620                                         xscale->high_vectors);
1621                 if (retval != ERROR_OK)
1622                         return retval;
1623
1624                 jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
1625
1626                 jtag_add_sleep(100000);
1627
1628                 /* set Hold reset, Halt mode and Trap Reset */
1629                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1630                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1631                 xscale_write_dcsr(target, 1, 0);
1632
1633                 /* clear Hold reset to let the target run (should enter debug handler) */
1634                 xscale_write_dcsr(target, 0, 1);
1635                 target->state = TARGET_RUNNING;
1636
1637                 if (!target->reset_halt)
1638                 {
1639                         jtag_add_sleep(10000);
1640
1641                         /* we should have entered debug now */
1642                         xscale_debug_entry(target);
1643                         target->state = TARGET_HALTED;
1644
1645                         /* resume the target */
1646                         xscale_resume(target, 1, 0x0, 1, 0);
1647                 }
1648         }
1649
1650         return ERROR_OK;
1651 }
1652
1653 static int xscale_read_core_reg(struct target *target, int num,
1654                 enum armv4_5_mode mode)
1655 {
1656         LOG_ERROR("not implemented");
1657         return ERROR_OK;
1658 }
1659
1660 static int xscale_write_core_reg(struct target *target, int num,
1661                 enum armv4_5_mode mode, uint32_t value)
1662 {
1663         LOG_ERROR("not implemented");
1664         return ERROR_OK;
1665 }
1666
1667 static int xscale_full_context(struct target *target)
1668 {
1669         struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
1670
1671         uint32_t *buffer;
1672
1673         int i, j;
1674
1675         LOG_DEBUG("-");
1676
1677         if (target->state != TARGET_HALTED)
1678         {
1679                 LOG_WARNING("target not halted");
1680                 return ERROR_TARGET_NOT_HALTED;
1681         }
1682
1683         buffer = malloc(4 * 8);
1684
1685         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1686          * we can't enter User mode on an XScale (unpredictable),
1687          * but User shares registers with SYS
1688          */
1689         for (i = 1; i < 7; i++)
1690         {
1691                 int valid = 1;
1692
1693                 /* check if there are invalid registers in the current mode
1694                  */
1695                 for (j = 0; j <= 16; j++)
1696                 {
1697                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1698                                 valid = 0;
1699                 }
1700
1701                 if (!valid)
1702                 {
1703                         uint32_t tmp_cpsr;
1704
1705                         /* request banked registers */
1706                         xscale_send_u32(target, 0x0);
1707
1708                         tmp_cpsr = 0x0;
1709                         tmp_cpsr |= armv4_5_number_to_mode(i);
1710                         tmp_cpsr |= 0xc0; /* I/F bits */
1711
1712                         /* send CPSR for desired mode */
1713                         xscale_send_u32(target, tmp_cpsr);
1714
1715                         /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1716                         if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1717                         {
1718                                 xscale_receive(target, buffer, 8);
1719                                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, buffer[7]);
1720                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1721                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1722                         }
1723                         else
1724                         {
1725                                 xscale_receive(target, buffer, 7);
1726                         }
1727
1728                         /* move data from buffer to register cache */
1729                         for (j = 8; j <= 14; j++)
1730                         {
1731                                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value, 0, 32, buffer[j - 8]);
1732                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1733                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1734                         }
1735                 }
1736         }
1737
1738         free(buffer);
1739
1740         return ERROR_OK;
1741 }
1742
1743 static int xscale_restore_context(struct target *target)
1744 {
1745         struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
1746
1747         int i, j;
1748
1749         if (target->state != TARGET_HALTED)
1750         {
1751                 LOG_WARNING("target not halted");
1752                 return ERROR_TARGET_NOT_HALTED;
1753         }
1754
1755         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1756         * we can't enter User mode on an XScale (unpredictable),
1757         * but User shares registers with SYS
1758         */
1759         for (i = 1; i < 7; i++)
1760         {
1761                 int dirty = 0;
1762
1763                 /* check if there are invalid registers in the current mode
1764                 */
1765                 for (j = 8; j <= 14; j++)
1766                 {
1767                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty == 1)
1768                                 dirty = 1;
1769                 }
1770
1771                 /* if not USR/SYS, check if the SPSR needs to be written */
1772                 if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1773                 {
1774                         if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty == 1)
1775                                 dirty = 1;
1776                 }
1777
1778                 if (dirty)
1779                 {
1780                         uint32_t tmp_cpsr;
1781
1782                         /* send banked registers */
1783                         xscale_send_u32(target, 0x1);
1784
1785                         tmp_cpsr = 0x0;
1786                         tmp_cpsr |= armv4_5_number_to_mode(i);
1787                         tmp_cpsr |= 0xc0; /* I/F bits */
1788
1789                         /* send CPSR for desired mode */
1790                         xscale_send_u32(target, tmp_cpsr);
1791
1792                         /* send banked registers, r8 to r14, and spsr if not in USR/SYS mode */
1793                         for (j = 8; j <= 14; j++)
1794                         {
1795                                 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, j).value, 0, 32));
1796                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1797                         }
1798
1799                         if ((armv4_5_number_to_mode(i) != ARMV4_5_MODE_USR) && (armv4_5_number_to_mode(i) != ARMV4_5_MODE_SYS))
1800                         {
1801                                 xscale_send_u32(target, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32));
1802                                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1803                         }
1804                 }
1805         }
1806
1807         return ERROR_OK;
1808 }
1809
1810 static int xscale_read_memory(struct target *target, uint32_t address,
1811                 uint32_t size, uint32_t count, uint8_t *buffer)
1812 {
1813         struct xscale_common *xscale = target_to_xscale(target);
1814         uint32_t *buf32;
1815         uint32_t i;
1816         int retval;
1817
1818         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1819
1820         if (target->state != TARGET_HALTED)
1821         {
1822                 LOG_WARNING("target not halted");
1823                 return ERROR_TARGET_NOT_HALTED;
1824         }
1825
1826         /* sanitize arguments */
1827         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1828                 return ERROR_INVALID_ARGUMENTS;
1829
1830         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1831                 return ERROR_TARGET_UNALIGNED_ACCESS;
1832
1833         /* send memory read request (command 0x1n, n: access size) */
1834         if ((retval = xscale_send_u32(target, 0x10 | size)) != ERROR_OK)
1835                 return retval;
1836
1837         /* send base address for read request */
1838         if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1839                 return retval;
1840
1841         /* send number of requested data words */
1842         if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1843                 return retval;
1844
1845         /* receive data from target (count times 32-bit words in host endianness) */
1846         buf32 = malloc(4 * count);
1847         if ((retval = xscale_receive(target, buf32, count)) != ERROR_OK)
1848                 return retval;
1849
1850         /* extract data from host-endian buffer into byte stream */
1851         for (i = 0; i < count; i++)
1852         {
1853                 switch (size)
1854                 {
1855                         case 4:
1856                                 target_buffer_set_u32(target, buffer, buf32[i]);
1857                                 buffer += 4;
1858                                 break;
1859                         case 2:
1860                                 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1861                                 buffer += 2;
1862                                 break;
1863                         case 1:
1864                                 *buffer++ = buf32[i] & 0xff;
1865                                 break;
1866                         default:
1867                                 LOG_ERROR("should never get here");
1868                                 exit(-1);
1869                 }
1870         }
1871
1872         free(buf32);
1873
1874         /* examine DCSR, to see if Sticky Abort (SA) got set */
1875         if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1876                 return retval;
1877         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1878         {
1879                 /* clear SA bit */
1880                 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1881                         return retval;
1882
1883                 return ERROR_TARGET_DATA_ABORT;
1884         }
1885
1886         return ERROR_OK;
1887 }
1888
1889 static int xscale_write_memory(struct target *target, uint32_t address,
1890                 uint32_t size, uint32_t count, uint8_t *buffer)
1891 {
1892         struct xscale_common *xscale = target_to_xscale(target);
1893         int retval;
1894
1895         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32, address, size, count);
1896
1897         if (target->state != TARGET_HALTED)
1898         {
1899                 LOG_WARNING("target not halted");
1900                 return ERROR_TARGET_NOT_HALTED;
1901         }
1902
1903         /* sanitize arguments */
1904         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1905                 return ERROR_INVALID_ARGUMENTS;
1906
1907         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1908                 return ERROR_TARGET_UNALIGNED_ACCESS;
1909
1910         /* send memory write request (command 0x2n, n: access size) */
1911         if ((retval = xscale_send_u32(target, 0x20 | size)) != ERROR_OK)
1912                 return retval;
1913
1914         /* send base address for read request */
1915         if ((retval = xscale_send_u32(target, address)) != ERROR_OK)
1916                 return retval;
1917
1918         /* send number of requested data words to be written*/
1919         if ((retval = xscale_send_u32(target, count)) != ERROR_OK)
1920                 return retval;
1921
1922         /* extract data from host-endian buffer into byte stream */
1923 #if 0
1924         for (i = 0; i < count; i++)
1925         {
1926                 switch (size)
1927                 {
1928                         case 4:
1929                                 value = target_buffer_get_u32(target, buffer);
1930                                 xscale_send_u32(target, value);
1931                                 buffer += 4;
1932                                 break;
1933                         case 2:
1934                                 value = target_buffer_get_u16(target, buffer);
1935                                 xscale_send_u32(target, value);
1936                                 buffer += 2;
1937                                 break;
1938                         case 1:
1939                                 value = *buffer;
1940                                 xscale_send_u32(target, value);
1941                                 buffer += 1;
1942                                 break;
1943                         default:
1944                                 LOG_ERROR("should never get here");
1945                                 exit(-1);
1946                 }
1947         }
1948 #endif
1949         if ((retval = xscale_send(target, buffer, count, size)) != ERROR_OK)
1950                 return retval;
1951
1952         /* examine DCSR, to see if Sticky Abort (SA) got set */
1953         if ((retval = xscale_read_dcsr(target)) != ERROR_OK)
1954                 return retval;
1955         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1)
1956         {
1957                 /* clear SA bit */
1958                 if ((retval = xscale_send_u32(target, 0x60)) != ERROR_OK)
1959                         return retval;
1960
1961                 return ERROR_TARGET_DATA_ABORT;
1962         }
1963
1964         return ERROR_OK;
1965 }
1966
1967 static int xscale_bulk_write_memory(struct target *target, uint32_t address,
1968                 uint32_t count, uint8_t *buffer)
1969 {
1970         return xscale_write_memory(target, address, 4, count, buffer);
1971 }
1972
1973 static uint32_t xscale_get_ttb(struct target *target)
1974 {
1975         struct xscale_common *xscale = target_to_xscale(target);
1976         uint32_t ttb;
1977
1978         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
1979         ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
1980
1981         return ttb;
1982 }
1983
1984 static void xscale_disable_mmu_caches(struct target *target, int mmu,
1985                 int d_u_cache, int i_cache)
1986 {
1987         struct xscale_common *xscale = target_to_xscale(target);
1988         uint32_t cp15_control;
1989
1990         /* read cp15 control register */
1991         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1992         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1993
1994         if (mmu)
1995                 cp15_control &= ~0x1U;
1996
1997         if (d_u_cache)
1998         {
1999                 /* clean DCache */
2000                 xscale_send_u32(target, 0x50);
2001                 xscale_send_u32(target, xscale->cache_clean_address);
2002
2003                 /* invalidate DCache */
2004                 xscale_send_u32(target, 0x51);
2005
2006                 cp15_control &= ~0x4U;
2007         }
2008
2009         if (i_cache)
2010         {
2011                 /* invalidate ICache */
2012                 xscale_send_u32(target, 0x52);
2013                 cp15_control &= ~0x1000U;
2014         }
2015
2016         /* write new cp15 control register */
2017         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2018
2019         /* execute cpwait to ensure outstanding operations complete */
2020         xscale_send_u32(target, 0x53);
2021 }
2022
2023 static void xscale_enable_mmu_caches(struct target *target, int mmu,
2024                 int d_u_cache, int i_cache)
2025 {
2026         struct xscale_common *xscale = target_to_xscale(target);
2027         uint32_t cp15_control;
2028
2029         /* read cp15 control register */
2030         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2031         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2032
2033         if (mmu)
2034                 cp15_control |= 0x1U;
2035
2036         if (d_u_cache)
2037                 cp15_control |= 0x4U;
2038
2039         if (i_cache)
2040                 cp15_control |= 0x1000U;
2041
2042         /* write new cp15 control register */
2043         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2044
2045         /* execute cpwait to ensure outstanding operations complete */
2046         xscale_send_u32(target, 0x53);
2047 }
2048
2049 static int xscale_set_breakpoint(struct target *target,
2050                 struct breakpoint *breakpoint)
2051 {
2052         int retval;
2053         struct xscale_common *xscale = target_to_xscale(target);
2054
2055         if (target->state != TARGET_HALTED)
2056         {
2057                 LOG_WARNING("target not halted");
2058                 return ERROR_TARGET_NOT_HALTED;
2059         }
2060
2061         if (breakpoint->set)
2062         {
2063                 LOG_WARNING("breakpoint already set");
2064                 return ERROR_OK;
2065         }
2066
2067         if (breakpoint->type == BKPT_HARD)
2068         {
2069                 uint32_t value = breakpoint->address | 1;
2070                 if (!xscale->ibcr0_used)
2071                 {
2072                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2073                         xscale->ibcr0_used = 1;
2074                         breakpoint->set = 1;    /* breakpoint set on first breakpoint register */
2075                 }
2076                 else if (!xscale->ibcr1_used)
2077                 {
2078                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2079                         xscale->ibcr1_used = 1;
2080                         breakpoint->set = 2;    /* breakpoint set on second breakpoint register */
2081                 }
2082                 else
2083                 {
2084                         LOG_ERROR("BUG: no hardware comparator available");
2085                         return ERROR_OK;
2086                 }
2087         }
2088         else if (breakpoint->type == BKPT_SOFT)
2089         {
2090                 if (breakpoint->length == 4)
2091                 {
2092                         /* keep the original instruction in target endianness */
2093                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2094                         {
2095                                 return retval;
2096                         }
2097                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2098                         if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
2099                         {
2100                                 return retval;
2101                         }
2102                 }
2103                 else
2104                 {
2105                         /* keep the original instruction in target endianness */
2106                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2107                         {
2108                                 return retval;
2109                         }
2110                         /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
2111                         if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
2112                         {
2113                                 return retval;
2114                         }
2115                 }
2116                 breakpoint->set = 1;
2117         }
2118
2119         return ERROR_OK;
2120 }
2121
2122 static int xscale_add_breakpoint(struct target *target,
2123                 struct breakpoint *breakpoint)
2124 {
2125         struct xscale_common *xscale = target_to_xscale(target);
2126
2127         if (target->state != TARGET_HALTED)
2128         {
2129                 LOG_WARNING("target not halted");
2130                 return ERROR_TARGET_NOT_HALTED;
2131         }
2132
2133         if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
2134         {
2135                 LOG_INFO("no breakpoint unit available for hardware breakpoint");
2136                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2137         }
2138
2139         if ((breakpoint->length != 2) && (breakpoint->length != 4))
2140         {
2141                 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2142                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2143         }
2144
2145         if (breakpoint->type == BKPT_HARD)
2146         {
2147                 xscale->ibcr_available--;
2148         }
2149
2150         return ERROR_OK;
2151 }
2152
2153 static int xscale_unset_breakpoint(struct target *target,
2154                 struct breakpoint *breakpoint)
2155 {
2156         int retval;
2157         struct xscale_common *xscale = target_to_xscale(target);
2158
2159         if (target->state != TARGET_HALTED)
2160         {
2161                 LOG_WARNING("target not halted");
2162                 return ERROR_TARGET_NOT_HALTED;
2163         }
2164
2165         if (!breakpoint->set)
2166         {
2167                 LOG_WARNING("breakpoint not set");
2168                 return ERROR_OK;
2169         }
2170
2171         if (breakpoint->type == BKPT_HARD)
2172         {
2173                 if (breakpoint->set == 1)
2174                 {
2175                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2176                         xscale->ibcr0_used = 0;
2177                 }
2178                 else if (breakpoint->set == 2)
2179                 {
2180                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2181                         xscale->ibcr1_used = 0;
2182                 }
2183                 breakpoint->set = 0;
2184         }
2185         else
2186         {
2187                 /* restore original instruction (kept in target endianness) */
2188                 if (breakpoint->length == 4)
2189                 {
2190                         if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
2191                         {
2192                                 return retval;
2193                         }
2194                 }
2195                 else
2196                 {
2197                         if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
2198                         {
2199                                 return retval;
2200                         }
2201                 }
2202                 breakpoint->set = 0;
2203         }
2204
2205         return ERROR_OK;
2206 }
2207
2208 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2209 {
2210         struct xscale_common *xscale = target_to_xscale(target);
2211
2212         if (target->state != TARGET_HALTED)
2213         {
2214                 LOG_WARNING("target not halted");
2215                 return ERROR_TARGET_NOT_HALTED;
2216         }
2217
2218         if (breakpoint->set)
2219         {
2220                 xscale_unset_breakpoint(target, breakpoint);
2221         }
2222
2223         if (breakpoint->type == BKPT_HARD)
2224                 xscale->ibcr_available++;
2225
2226         return ERROR_OK;
2227 }
2228
2229 static int xscale_set_watchpoint(struct target *target,
2230                 struct watchpoint *watchpoint)
2231 {
2232         struct xscale_common *xscale = target_to_xscale(target);
2233         uint8_t enable = 0;
2234         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2235         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2236
2237         if (target->state != TARGET_HALTED)
2238         {
2239                 LOG_WARNING("target not halted");
2240                 return ERROR_TARGET_NOT_HALTED;
2241         }
2242
2243         xscale_get_reg(dbcon);
2244
2245         switch (watchpoint->rw)
2246         {
2247                 case WPT_READ:
2248                         enable = 0x3;
2249                         break;
2250                 case WPT_ACCESS:
2251                         enable = 0x2;
2252                         break;
2253                 case WPT_WRITE:
2254                         enable = 0x1;
2255                         break;
2256                 default:
2257                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2258         }
2259
2260         if (!xscale->dbr0_used)
2261         {
2262                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2263                 dbcon_value |= enable;
2264                 xscale_set_reg_u32(dbcon, dbcon_value);
2265                 watchpoint->set = 1;
2266                 xscale->dbr0_used = 1;
2267         }
2268         else if (!xscale->dbr1_used)
2269         {
2270                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2271                 dbcon_value |= enable << 2;
2272                 xscale_set_reg_u32(dbcon, dbcon_value);
2273                 watchpoint->set = 2;
2274                 xscale->dbr1_used = 1;
2275         }
2276         else
2277         {
2278                 LOG_ERROR("BUG: no hardware comparator available");
2279                 return ERROR_OK;
2280         }
2281
2282         return ERROR_OK;
2283 }
2284
2285 static int xscale_add_watchpoint(struct target *target,
2286                 struct watchpoint *watchpoint)
2287 {
2288         struct xscale_common *xscale = target_to_xscale(target);
2289
2290         if (target->state != TARGET_HALTED)
2291         {
2292                 LOG_WARNING("target not halted");
2293                 return ERROR_TARGET_NOT_HALTED;
2294         }
2295
2296         if (xscale->dbr_available < 1)
2297         {
2298                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2299         }
2300
2301         if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
2302         {
2303                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2304         }
2305
2306         xscale->dbr_available--;
2307
2308         return ERROR_OK;
2309 }
2310
2311 static int xscale_unset_watchpoint(struct target *target,
2312                 struct watchpoint *watchpoint)
2313 {
2314         struct xscale_common *xscale = target_to_xscale(target);
2315         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2316         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2317
2318         if (target->state != TARGET_HALTED)
2319         {
2320                 LOG_WARNING("target not halted");
2321                 return ERROR_TARGET_NOT_HALTED;
2322         }
2323
2324         if (!watchpoint->set)
2325         {
2326                 LOG_WARNING("breakpoint not set");
2327                 return ERROR_OK;
2328         }
2329
2330         if (watchpoint->set == 1)
2331         {
2332                 dbcon_value &= ~0x3;
2333                 xscale_set_reg_u32(dbcon, dbcon_value);
2334                 xscale->dbr0_used = 0;
2335         }
2336         else if (watchpoint->set == 2)
2337         {
2338                 dbcon_value &= ~0xc;
2339                 xscale_set_reg_u32(dbcon, dbcon_value);
2340                 xscale->dbr1_used = 0;
2341         }
2342         watchpoint->set = 0;
2343
2344         return ERROR_OK;
2345 }
2346
2347 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2348 {
2349         struct xscale_common *xscale = target_to_xscale(target);
2350
2351         if (target->state != TARGET_HALTED)
2352         {
2353                 LOG_WARNING("target not halted");
2354                 return ERROR_TARGET_NOT_HALTED;
2355         }
2356
2357         if (watchpoint->set)
2358         {
2359                 xscale_unset_watchpoint(target, watchpoint);
2360         }
2361
2362         xscale->dbr_available++;
2363
2364         return ERROR_OK;
2365 }
2366
2367 static int xscale_get_reg(struct reg *reg)
2368 {
2369         struct xscale_reg *arch_info = reg->arch_info;
2370         struct target *target = arch_info->target;
2371         struct xscale_common *xscale = target_to_xscale(target);
2372
2373         /* DCSR, TX and RX are accessible via JTAG */
2374         if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2375         {
2376                 return xscale_read_dcsr(arch_info->target);
2377         }
2378         else if (strcmp(reg->name, "XSCALE_TX") == 0)
2379         {
2380                 /* 1 = consume register content */
2381                 return xscale_read_tx(arch_info->target, 1);
2382         }
2383         else if (strcmp(reg->name, "XSCALE_RX") == 0)
2384         {
2385                 /* can't read from RX register (host -> debug handler) */
2386                 return ERROR_OK;
2387         }
2388         else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2389         {
2390                 /* can't (explicitly) read from TXRXCTRL register */
2391                 return ERROR_OK;
2392         }
2393         else /* Other DBG registers have to be transfered by the debug handler */
2394         {
2395                 /* send CP read request (command 0x40) */
2396                 xscale_send_u32(target, 0x40);
2397
2398                 /* send CP register number */
2399                 xscale_send_u32(target, arch_info->dbg_handler_number);
2400
2401                 /* read register value */
2402                 xscale_read_tx(target, 1);
2403                 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2404
2405                 reg->dirty = 0;
2406                 reg->valid = 1;
2407         }
2408
2409         return ERROR_OK;
2410 }
2411
2412 static int xscale_set_reg(struct reg *reg, uint8_t* buf)
2413 {
2414         struct xscale_reg *arch_info = reg->arch_info;
2415         struct target *target = arch_info->target;
2416         struct xscale_common *xscale = target_to_xscale(target);
2417         uint32_t value = buf_get_u32(buf, 0, 32);
2418
2419         /* DCSR, TX and RX are accessible via JTAG */
2420         if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2421         {
2422                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2423                 return xscale_write_dcsr(arch_info->target, -1, -1);
2424         }
2425         else if (strcmp(reg->name, "XSCALE_RX") == 0)
2426         {
2427                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2428                 return xscale_write_rx(arch_info->target);
2429         }
2430         else if (strcmp(reg->name, "XSCALE_TX") == 0)
2431         {
2432                 /* can't write to TX register (debug-handler -> host) */
2433                 return ERROR_OK;
2434         }
2435         else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0)
2436         {
2437                 /* can't (explicitly) write to TXRXCTRL register */
2438                 return ERROR_OK;
2439         }
2440         else /* Other DBG registers have to be transfered by the debug handler */
2441         {
2442                 /* send CP write request (command 0x41) */
2443                 xscale_send_u32(target, 0x41);
2444
2445                 /* send CP register number */
2446                 xscale_send_u32(target, arch_info->dbg_handler_number);
2447
2448                 /* send CP register value */
2449                 xscale_send_u32(target, value);
2450                 buf_set_u32(reg->value, 0, 32, value);
2451         }
2452
2453         return ERROR_OK;
2454 }
2455
2456 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2457 {
2458         struct xscale_common *xscale = target_to_xscale(target);
2459         struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2460         struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2461
2462         /* send CP write request (command 0x41) */
2463         xscale_send_u32(target, 0x41);
2464
2465         /* send CP register number */
2466         xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2467
2468         /* send CP register value */
2469         xscale_send_u32(target, value);
2470         buf_set_u32(dcsr->value, 0, 32, value);
2471
2472         return ERROR_OK;
2473 }
2474
2475 static int xscale_read_trace(struct target *target)
2476 {
2477         struct xscale_common *xscale = target_to_xscale(target);
2478         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
2479         struct xscale_trace_data **trace_data_p;
2480
2481         /* 258 words from debug handler
2482          * 256 trace buffer entries
2483          * 2 checkpoint addresses
2484          */
2485         uint32_t trace_buffer[258];
2486         int is_address[256];
2487         int i, j;
2488
2489         if (target->state != TARGET_HALTED)
2490         {
2491                 LOG_WARNING("target must be stopped to read trace data");
2492                 return ERROR_TARGET_NOT_HALTED;
2493         }
2494
2495         /* send read trace buffer command (command 0x61) */
2496         xscale_send_u32(target, 0x61);
2497
2498         /* receive trace buffer content */
2499         xscale_receive(target, trace_buffer, 258);
2500
2501         /* parse buffer backwards to identify address entries */
2502         for (i = 255; i >= 0; i--)
2503         {
2504                 is_address[i] = 0;
2505                 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2506                         ((trace_buffer[i] & 0xf0) == 0xd0))
2507                 {
2508                         if (i >= 3)
2509                                 is_address[--i] = 1;
2510                         if (i >= 2)
2511                                 is_address[--i] = 1;
2512                         if (i >= 1)
2513                                 is_address[--i] = 1;
2514                         if (i >= 0)
2515                                 is_address[--i] = 1;
2516                 }
2517         }
2518
2519
2520         /* search first non-zero entry */
2521         for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2522                 ;
2523
2524         if (j == 256)
2525         {
2526                 LOG_DEBUG("no trace data collected");
2527                 return ERROR_XSCALE_NO_TRACE_DATA;
2528         }
2529
2530         for (trace_data_p = &xscale->trace.data; *trace_data_p; trace_data_p = &(*trace_data_p)->next)
2531                 ;
2532
2533         *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2534         (*trace_data_p)->next = NULL;
2535         (*trace_data_p)->chkpt0 = trace_buffer[256];
2536         (*trace_data_p)->chkpt1 = trace_buffer[257];
2537         (*trace_data_p)->last_instruction = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2538         (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2539         (*trace_data_p)->depth = 256 - j;
2540
2541         for (i = j; i < 256; i++)
2542         {
2543                 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2544                 if (is_address[i])
2545                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2546                 else
2547                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2548         }
2549
2550         return ERROR_OK;
2551 }
2552
2553 static int xscale_read_instruction(struct target *target,
2554                 struct arm_instruction *instruction)
2555 {
2556         struct xscale_common *xscale = target_to_xscale(target);
2557         int i;
2558         int section = -1;
2559         uint32_t size_read;
2560         uint32_t opcode;
2561         int retval;
2562
2563         if (!xscale->trace.image)
2564                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2565
2566         /* search for the section the current instruction belongs to */
2567         for (i = 0; i < xscale->trace.image->num_sections; i++)
2568         {
2569                 if ((xscale->trace.image->sections[i].base_address <= xscale->trace.current_pc) &&
2570                         (xscale->trace.image->sections[i].base_address + xscale->trace.image->sections[i].size > xscale->trace.current_pc))
2571                 {
2572                         section = i;
2573                         break;
2574                 }
2575         }
2576
2577         if (section == -1)
2578         {
2579                 /* current instruction couldn't be found in the image */
2580                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2581         }
2582
2583         if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
2584         {
2585                 uint8_t buf[4];
2586                 if ((retval = image_read_section(xscale->trace.image, section,
2587                         xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2588                         4, buf, &size_read)) != ERROR_OK)
2589                 {
2590                         LOG_ERROR("error while reading instruction: %i", retval);
2591                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2592                 }
2593                 opcode = target_buffer_get_u32(target, buf);
2594                 arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2595         }
2596         else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
2597         {
2598                 uint8_t buf[2];
2599                 if ((retval = image_read_section(xscale->trace.image, section,
2600                         xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2601                         2, buf, &size_read)) != ERROR_OK)
2602                 {
2603                         LOG_ERROR("error while reading instruction: %i", retval);
2604                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2605                 }
2606                 opcode = target_buffer_get_u16(target, buf);
2607                 thumb_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
2608         }
2609         else
2610         {
2611                 LOG_ERROR("BUG: unknown core state encountered");
2612                 exit(-1);
2613         }
2614
2615         return ERROR_OK;
2616 }
2617
2618 static int xscale_branch_address(struct xscale_trace_data *trace_data,
2619                 int i, uint32_t *target)
2620 {
2621         /* if there are less than four entries prior to the indirect branch message
2622          * we can't extract the address */
2623         if (i < 4)
2624         {
2625                 return -1;
2626         }
2627
2628         *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2629                                 (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2630
2631         return 0;
2632 }
2633
2634 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2635 {
2636         struct xscale_common *xscale = target_to_xscale(target);
2637         int next_pc_ok = 0;
2638         uint32_t next_pc = 0x0;
2639         struct xscale_trace_data *trace_data = xscale->trace.data;
2640         int retval;
2641
2642         while (trace_data)
2643         {
2644                 int i, chkpt;
2645                 int rollover;
2646                 int branch;
2647                 int exception;
2648                 xscale->trace.core_state = ARMV4_5_STATE_ARM;
2649
2650                 chkpt = 0;
2651                 rollover = 0;
2652
2653                 for (i = 0; i < trace_data->depth; i++)
2654                 {
2655                         next_pc_ok = 0;
2656                         branch = 0;
2657                         exception = 0;
2658
2659                         if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2660                                 continue;
2661
2662                         switch ((trace_data->entries[i].data & 0xf0) >> 4)
2663                         {
2664                                 case 0:         /* Exceptions */
2665                                 case 1:
2666                                 case 2:
2667                                 case 3:
2668                                 case 4:
2669                                 case 5:
2670                                 case 6:
2671                                 case 7:
2672                                         exception = (trace_data->entries[i].data & 0x70) >> 4;
2673                                         next_pc_ok = 1;
2674                                         next_pc = (trace_data->entries[i].data & 0xf0) >> 2;
2675                                         command_print(cmd_ctx, "--- exception %i ---", (trace_data->entries[i].data & 0xf0) >> 4);
2676                                         break;
2677                                 case 8:         /* Direct Branch */
2678                                         branch = 1;
2679                                         break;
2680                                 case 9:         /* Indirect Branch */
2681                                         branch = 1;
2682                                         if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2683                                         {
2684                                                 next_pc_ok = 1;
2685                                         }
2686                                         break;
2687                                 case 13:        /* Checkpointed Indirect Branch */
2688                                         if (xscale_branch_address(trace_data, i, &next_pc) == 0)
2689                                         {
2690                                                 next_pc_ok = 1;
2691                                                 if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
2692                                                         || ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
2693                                                         LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
2694                                         }
2695                                         /* explicit fall-through */
2696                                 case 12:        /* Checkpointed Direct Branch */
2697                                         branch = 1;
2698                                         if (chkpt == 0)
2699                                         {
2700                                                 next_pc_ok = 1;
2701                                                 next_pc = trace_data->chkpt0;
2702                                                 chkpt++;
2703                                         }
2704                                         else if (chkpt == 1)
2705                                         {
2706                                                 next_pc_ok = 1;
2707                                                 next_pc = trace_data->chkpt0;
2708                                                 chkpt++;
2709                                         }
2710                                         else
2711                                         {
2712                                                 LOG_WARNING("more than two checkpointed branches encountered");
2713                                         }
2714                                         break;
2715                                 case 15:        /* Roll-over */
2716                                         rollover++;
2717                                         continue;
2718                                 default:        /* Reserved */
2719                                         command_print(cmd_ctx, "--- reserved trace message ---");
2720                                         LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
2721                                         return ERROR_OK;
2722                         }
2723
2724                         if (xscale->trace.pc_ok)
2725                         {
2726                                 int executed = (trace_data->entries[i].data & 0xf) + rollover * 16;
2727                                 struct arm_instruction instruction;
2728
2729                                 if ((exception == 6) || (exception == 7))
2730                                 {
2731                                         /* IRQ or FIQ exception, no instruction executed */
2732                                         executed -= 1;
2733                                 }
2734
2735                                 while (executed-- >= 0)
2736                                 {
2737                                         if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2738                                         {
2739                                                 /* can't continue tracing with no image available */
2740                                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2741                                                 {
2742                                                         return retval;
2743                                                 }
2744                                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2745                                                 {
2746                                                         /* TODO: handle incomplete images */
2747                                                 }
2748                                         }
2749
2750                                         /* a precise abort on a load to the PC is included in the incremental
2751                                          * word count, other instructions causing data aborts are not included
2752                                          */
2753                                         if ((executed == 0) && (exception == 4)
2754                                                 && ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDM)))
2755                                         {
2756                                                 if ((instruction.type == ARM_LDM)
2757                                                         && ((instruction.info.load_store_multiple.register_list & 0x8000) == 0))
2758                                                 {
2759                                                         executed--;
2760                                                 }
2761                                                 else if (((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
2762                                                         && (instruction.info.load_store.Rd != 15))
2763                                                 {
2764                                                         executed--;
2765                                                 }
2766                                         }
2767
2768                                         /* only the last instruction executed
2769                                          * (the one that caused the control flow change)
2770                                          * could be a taken branch
2771                                          */
2772                                         if (((executed == -1) && (branch == 1)) &&
2773                                                 (((instruction.type == ARM_B) ||
2774                                                         (instruction.type == ARM_BL) ||
2775                                                         (instruction.type == ARM_BLX)) &&
2776                                                         (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)))
2777                                         {
2778                                                 xscale->trace.current_pc = instruction.info.b_bl_bx_blx.target_address;
2779                                         }
2780                                         else
2781                                         {
2782                                                 xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
2783                                         }
2784                                         command_print(cmd_ctx, "%s", instruction.text);
2785                                 }
2786
2787                                 rollover = 0;
2788                         }
2789
2790                         if (next_pc_ok)
2791                         {
2792                                 xscale->trace.current_pc = next_pc;
2793                                 xscale->trace.pc_ok = 1;
2794                         }
2795                 }
2796
2797                 for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
2798                 {
2799                         struct arm_instruction instruction;
2800                         if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
2801                         {
2802                                 /* can't continue tracing with no image available */
2803                                 if (retval == ERROR_TRACE_IMAGE_UNAVAILABLE)
2804                                 {
2805                                         return retval;
2806                                 }
2807                                 else if (retval == ERROR_TRACE_INSTRUCTION_UNAVAILABLE)
2808                                 {
2809                                         /* TODO: handle incomplete images */
2810                                 }
2811                         }
2812                         command_print(cmd_ctx, "%s", instruction.text);
2813                 }
2814
2815                 trace_data = trace_data->next;
2816         }
2817
2818         return ERROR_OK;
2819 }
2820
2821 static void xscale_build_reg_cache(struct target *target)
2822 {
2823         struct xscale_common *xscale = target_to_xscale(target);
2824         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
2825         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2826         struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2827         int i;
2828         int num_regs = sizeof(xscale_reg_arch_info) / sizeof(struct xscale_reg);
2829
2830         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
2831         armv4_5->core_cache = (*cache_p);
2832
2833         /* register a register arch-type for XScale dbg registers only once */
2834         if (xscale_reg_arch_type == -1)
2835                 xscale_reg_arch_type = register_reg_arch_type(xscale_get_reg, xscale_set_reg);
2836
2837         (*cache_p)->next = malloc(sizeof(struct reg_cache));
2838         cache_p = &(*cache_p)->next;
2839
2840         /* fill in values for the xscale reg cache */
2841         (*cache_p)->name = "XScale registers";
2842         (*cache_p)->next = NULL;
2843         (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
2844         (*cache_p)->num_regs = num_regs;
2845
2846         for (i = 0; i < num_regs; i++)
2847         {
2848                 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2849                 (*cache_p)->reg_list[i].value = calloc(4, 1);
2850                 (*cache_p)->reg_list[i].dirty = 0;
2851                 (*cache_p)->reg_list[i].valid = 0;
2852                 (*cache_p)->reg_list[i].size = 32;
2853                 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2854                 (*cache_p)->reg_list[i].arch_type = xscale_reg_arch_type;
2855                 arch_info[i] = xscale_reg_arch_info[i];
2856                 arch_info[i].target = target;
2857         }
2858
2859         xscale->reg_cache = (*cache_p);
2860 }
2861
2862 static int xscale_init_target(struct command_context *cmd_ctx,
2863                 struct target *target)
2864 {
2865         xscale_build_reg_cache(target);
2866         return ERROR_OK;
2867 }
2868
2869 static int xscale_init_arch_info(struct target *target,
2870                 struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
2871 {
2872         struct arm *armv4_5;
2873         uint32_t high_reset_branch, low_reset_branch;
2874         int i;
2875
2876         armv4_5 = &xscale->armv4_5_common;
2877
2878         /* store architecture specfic data (none so far) */
2879         xscale->common_magic = XSCALE_COMMON_MAGIC;
2880
2881         /* we don't really *need* variant info ... */
2882         if (variant) {
2883                 int ir_length = 0;
2884
2885                 if (strcmp(variant, "pxa250") == 0
2886                                 || strcmp(variant, "pxa255") == 0
2887                                 || strcmp(variant, "pxa26x") == 0)
2888                         ir_length = 5;
2889                 else if (strcmp(variant, "pxa27x") == 0
2890                                 || strcmp(variant, "ixp42x") == 0
2891                                 || strcmp(variant, "ixp45x") == 0
2892                                 || strcmp(variant, "ixp46x") == 0)
2893                         ir_length = 7;
2894                 else
2895                         LOG_WARNING("%s: unrecognized variant %s",
2896                                 tap->dotted_name, variant);
2897
2898                 if (ir_length && ir_length != tap->ir_length) {
2899                         LOG_WARNING("%s: IR length for %s is %d; fixing",
2900                                 tap->dotted_name, variant, ir_length);
2901                         tap->ir_length = ir_length;
2902                 }
2903         }
2904
2905         /* the debug handler isn't installed (and thus not running) at this time */
2906         xscale->handler_address = 0xfe000800;
2907
2908         /* clear the vectors we keep locally for reference */
2909         memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
2910         memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
2911
2912         /* no user-specified vectors have been configured yet */
2913         xscale->static_low_vectors_set = 0x0;
2914         xscale->static_high_vectors_set = 0x0;
2915
2916         /* calculate branches to debug handler */
2917         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
2918         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2919
2920         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
2921         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
2922
2923         for (i = 1; i <= 7; i++)
2924         {
2925                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2926                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2927         }
2928
2929         /* 64kB aligned region used for DCache cleaning */
2930         xscale->cache_clean_address = 0xfffe0000;
2931
2932         xscale->hold_rst = 0;
2933         xscale->external_debug_break = 0;
2934
2935         xscale->ibcr_available = 2;
2936         xscale->ibcr0_used = 0;
2937         xscale->ibcr1_used = 0;
2938
2939         xscale->dbr_available = 2;
2940         xscale->dbr0_used = 0;
2941         xscale->dbr1_used = 0;
2942
2943         xscale->arm_bkpt = ARMV5_BKPT(0x0);
2944         xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
2945
2946         xscale->vector_catch = 0x1;
2947
2948         xscale->trace.capture_status = TRACE_IDLE;
2949         xscale->trace.data = NULL;
2950         xscale->trace.image = NULL;
2951         xscale->trace.buffer_enabled = 0;
2952         xscale->trace.buffer_fill = 0;
2953
2954         /* prepare ARMv4/5 specific information */
2955         armv4_5->arch_info = xscale;
2956         armv4_5->read_core_reg = xscale_read_core_reg;
2957         armv4_5->write_core_reg = xscale_write_core_reg;
2958         armv4_5->full_context = xscale_full_context;
2959
2960         armv4_5_init_arch_info(target, armv4_5);
2961
2962         xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
2963         xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
2964         xscale->armv4_5_mmu.read_memory = xscale_read_memory;
2965         xscale->armv4_5_mmu.write_memory = xscale_write_memory;
2966         xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
2967         xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
2968         xscale->armv4_5_mmu.has_tiny_pages = 1;
2969         xscale->armv4_5_mmu.mmu_enabled = 0;
2970
2971         return ERROR_OK;
2972 }
2973
2974 static int xscale_target_create(struct target *target, Jim_Interp *interp)
2975 {
2976         struct xscale_common *xscale;
2977
2978         if (sizeof xscale_debug_handler - 1 > 0x800) {
2979                 LOG_ERROR("debug_handler.bin: larger than 2kb");
2980                 return ERROR_FAIL;
2981         }
2982
2983         xscale = calloc(1, sizeof(*xscale));
2984         if (!xscale)
2985                 return ERROR_FAIL;
2986
2987         return xscale_init_arch_info(target, xscale, target->tap,
2988                         target->variant);
2989 }
2990
2991 COMMAND_HANDLER(xscale_handle_debug_handler_command)
2992 {
2993         struct target *target = NULL;
2994         struct xscale_common *xscale;
2995         int retval;
2996         uint32_t handler_address;
2997
2998         if (argc < 2)
2999         {
3000                 LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
3001                 return ERROR_OK;
3002         }
3003
3004         if ((target = get_target(args[0])) == NULL)
3005         {
3006                 LOG_ERROR("target '%s' not defined", args[0]);
3007                 return ERROR_FAIL;
3008         }
3009
3010         xscale = target_to_xscale(target);
3011         retval = xscale_verify_pointer(cmd_ctx, xscale);
3012         if (retval != ERROR_OK)
3013                 return retval;
3014
3015         COMMAND_PARSE_NUMBER(u32, args[1], handler_address);
3016
3017         if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3018                 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3019         {
3020                 xscale->handler_address = handler_address;
3021         }
3022         else
3023         {
3024                 LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3025                 return ERROR_FAIL;
3026         }
3027
3028         return ERROR_OK;
3029 }
3030
3031 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3032 {
3033         struct target *target = NULL;
3034         struct xscale_common *xscale;
3035         int retval;
3036         uint32_t cache_clean_address;
3037
3038         if (argc < 2)
3039         {
3040                 return ERROR_COMMAND_SYNTAX_ERROR;
3041         }
3042
3043         target = get_target(args[0]);
3044         if (target == NULL)
3045         {
3046                 LOG_ERROR("target '%s' not defined", args[0]);
3047                 return ERROR_FAIL;
3048         }
3049         xscale = target_to_xscale(target);
3050         retval = xscale_verify_pointer(cmd_ctx, xscale);
3051         if (retval != ERROR_OK)
3052                 return retval;
3053
3054         COMMAND_PARSE_NUMBER(u32, args[1], cache_clean_address);
3055
3056         if (cache_clean_address & 0xffff)
3057         {
3058                 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3059         }
3060         else
3061         {
3062                 xscale->cache_clean_address = cache_clean_address;
3063         }
3064
3065         return ERROR_OK;
3066 }
3067
3068 COMMAND_HANDLER(xscale_handle_cache_info_command)
3069 {
3070         struct target *target = get_current_target(cmd_ctx);
3071         struct xscale_common *xscale = target_to_xscale(target);
3072         int retval;
3073
3074         retval = xscale_verify_pointer(cmd_ctx, xscale);
3075         if (retval != ERROR_OK)
3076                 return retval;
3077
3078         return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
3079 }
3080
3081 static int xscale_virt2phys(struct target *target,
3082                 uint32_t virtual, uint32_t *physical)
3083 {
3084         struct xscale_common *xscale = target_to_xscale(target);
3085         int type;
3086         uint32_t cb;
3087         int domain;
3088         uint32_t ap;
3089
3090         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3091                 LOG_ERROR(xscale_not);
3092                 return ERROR_TARGET_INVALID;
3093         }
3094
3095         uint32_t ret = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
3096         if (type == -1)
3097         {
3098                 return ret;
3099         }
3100         *physical = ret;
3101         return ERROR_OK;
3102 }
3103
3104 static int xscale_mmu(struct target *target, int *enabled)
3105 {
3106         struct xscale_common *xscale = target_to_xscale(target);
3107
3108         if (target->state != TARGET_HALTED)
3109         {
3110                 LOG_ERROR("Target not halted");
3111                 return ERROR_TARGET_INVALID;
3112         }
3113         *enabled = xscale->armv4_5_mmu.mmu_enabled;
3114         return ERROR_OK;
3115 }
3116
3117 COMMAND_HANDLER(xscale_handle_mmu_command)
3118 {
3119         struct target *target = get_current_target(cmd_ctx);
3120         struct xscale_common *xscale = target_to_xscale(target);
3121         int retval;
3122
3123         retval = xscale_verify_pointer(cmd_ctx, xscale);
3124         if (retval != ERROR_OK)
3125                 return retval;
3126
3127         if (target->state != TARGET_HALTED)
3128         {
3129                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
3130                 return ERROR_OK;
3131         }
3132
3133         if (argc >= 1)
3134         {
3135                 if (strcmp("enable", args[0]) == 0)
3136                 {
3137                         xscale_enable_mmu_caches(target, 1, 0, 0);
3138                         xscale->armv4_5_mmu.mmu_enabled = 1;
3139                 }
3140                 else if (strcmp("disable", args[0]) == 0)
3141                 {
3142                         xscale_disable_mmu_caches(target, 1, 0, 0);
3143                         xscale->armv4_5_mmu.mmu_enabled = 0;
3144                 }
3145         }
3146
3147         command_print(cmd_ctx, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3148
3149         return ERROR_OK;
3150 }
3151
3152 COMMAND_HANDLER(xscale_handle_idcache_command)
3153 {
3154         struct target *target = get_current_target(cmd_ctx);
3155         struct xscale_common *xscale = target_to_xscale(target);
3156         int icache = 0, dcache = 0;
3157         int retval;
3158
3159         retval = xscale_verify_pointer(cmd_ctx, xscale);
3160         if (retval != ERROR_OK)
3161                 return retval;
3162
3163         if (target->state != TARGET_HALTED)
3164         {
3165                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
3166                 return ERROR_OK;
3167         }
3168
3169         if (strcmp(CMD_NAME, "icache") == 0)
3170                 icache = 1;
3171         else if (strcmp(CMD_NAME, "dcache") == 0)
3172                 dcache = 1;
3173
3174         if (argc >= 1)
3175         {
3176                 if (strcmp("enable", args[0]) == 0)
3177                 {
3178                         xscale_enable_mmu_caches(target, 0, dcache, icache);
3179
3180                         if (icache)
3181                                 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
3182                         else if (dcache)
3183                                 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
3184                 }
3185                 else if (strcmp("disable", args[0]) == 0)
3186                 {
3187                         xscale_disable_mmu_caches(target, 0, dcache, icache);
3188
3189                         if (icache)
3190                                 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
3191                         else if (dcache)
3192                                 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
3193                 }
3194         }
3195
3196         if (icache)
3197                 command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
3198
3199         if (dcache)
3200                 command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
3201
3202         return ERROR_OK;
3203 }
3204
3205 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3206 {
3207         struct target *target = get_current_target(cmd_ctx);
3208         struct xscale_common *xscale = target_to_xscale(target);
3209         int retval;
3210
3211         retval = xscale_verify_pointer(cmd_ctx, xscale);
3212         if (retval != ERROR_OK)
3213                 return retval;
3214
3215         if (argc < 1)
3216         {
3217                 command_print(cmd_ctx, "usage: xscale vector_catch [mask]");
3218         }
3219         else
3220         {
3221                 COMMAND_PARSE_NUMBER(u8, args[0], xscale->vector_catch);
3222                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 8, xscale->vector_catch);
3223                 xscale_write_dcsr(target, -1, -1);
3224         }
3225
3226         command_print(cmd_ctx, "vector catch mask: 0x%2.2x", xscale->vector_catch);
3227
3228         return ERROR_OK;
3229 }
3230
3231
3232 COMMAND_HANDLER(xscale_handle_vector_table_command)
3233 {
3234         struct target *target = get_current_target(cmd_ctx);
3235         struct xscale_common *xscale = target_to_xscale(target);
3236         int err = 0;
3237         int retval;
3238
3239         retval = xscale_verify_pointer(cmd_ctx, xscale);
3240         if (retval != ERROR_OK)
3241                 return retval;
3242
3243         if (argc == 0) /* print current settings */
3244         {
3245                 int idx;
3246
3247                 command_print(cmd_ctx, "active user-set static vectors:");
3248                 for (idx = 1; idx < 8; idx++)
3249                         if (xscale->static_low_vectors_set & (1 << idx))
3250                                 command_print(cmd_ctx, "low  %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
3251                 for (idx = 1; idx < 8; idx++)
3252                         if (xscale->static_high_vectors_set & (1 << idx))
3253                                 command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
3254                 return ERROR_OK;
3255         }
3256
3257         if (argc != 3)
3258                 err = 1;
3259         else
3260         {
3261                 int idx;
3262                 COMMAND_PARSE_NUMBER(int, args[1], idx);
3263                 uint32_t vec;
3264                 COMMAND_PARSE_NUMBER(u32, args[2], vec);
3265
3266                 if (idx < 1 || idx >= 8)
3267                         err = 1;
3268
3269                 if (!err && strcmp(args[0], "low") == 0)
3270                 {
3271                         xscale->static_low_vectors_set |= (1<<idx);
3272                         xscale->static_low_vectors[idx] = vec;
3273                 }
3274                 else if (!err && (strcmp(args[0], "high") == 0))
3275                 {
3276                         xscale->static_high_vectors_set |= (1<<idx);
3277                         xscale->static_high_vectors[idx] = vec;
3278                 }
3279                 else
3280                         err = 1;
3281         }
3282
3283         if (err)
3284                 command_print(cmd_ctx, "usage: xscale vector_table <high|low> <index> <code>");
3285
3286         return ERROR_OK;
3287 }
3288
3289
3290 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3291 {
3292         struct target *target = get_current_target(cmd_ctx);
3293         struct xscale_common *xscale = target_to_xscale(target);
3294         struct armv4_5_common_s *armv4_5 = &xscale->armv4_5_common;
3295         uint32_t dcsr_value;
3296         int retval;
3297
3298         retval = xscale_verify_pointer(cmd_ctx, xscale);
3299         if (retval != ERROR_OK)
3300                 return retval;
3301
3302         if (target->state != TARGET_HALTED)
3303         {
3304                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
3305                 return ERROR_OK;
3306         }
3307
3308         if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
3309         {
3310                 struct xscale_trace_data *td, *next_td;
3311                 xscale->trace.buffer_enabled = 1;
3312
3313                 /* free old trace data */
3314                 td = xscale->trace.data;
3315                 while (td)
3316                 {
3317                         next_td = td->next;
3318
3319                         if (td->entries)
3320                                 free(td->entries);
3321                         free(td);
3322                         td = next_td;
3323                 }
3324                 xscale->trace.data = NULL;
3325         }
3326         else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
3327         {
3328                 xscale->trace.buffer_enabled = 0;
3329         }
3330
3331         if ((argc >= 2) && (strcmp("fill", args[1]) == 0))
3332         {
3333                 uint32_t fill = 1;
3334                 if (argc >= 3)
3335                         COMMAND_PARSE_NUMBER(u32, args[2], fill);
3336                 xscale->trace.buffer_fill = fill;
3337         }
3338         else if ((argc >= 2) && (strcmp("wrap", args[1]) == 0))
3339         {
3340                 xscale->trace.buffer_fill = -1;
3341         }
3342
3343         if (xscale->trace.buffer_enabled)
3344         {
3345                 /* if we enable the trace buffer in fill-once
3346                  * mode we know the address of the first instruction */
3347                 xscale->trace.pc_ok = 1;
3348                 xscale->trace.current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
3349         }
3350         else
3351         {
3352                 /* otherwise the address is unknown, and we have no known good PC */
3353                 xscale->trace.pc_ok = 0;
3354         }
3355
3356         command_print(cmd_ctx, "trace buffer %s (%s)",
3357                 (xscale->trace.buffer_enabled) ? "enabled" : "disabled",
3358                 (xscale->trace.buffer_fill > 0) ? "fill" : "wrap");
3359
3360         dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3361         if (xscale->trace.buffer_fill >= 0)
3362                 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3363         else
3364                 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3365
3366         return ERROR_OK;
3367 }
3368
3369 COMMAND_HANDLER(xscale_handle_trace_image_command)
3370 {
3371         struct target *target = get_current_target(cmd_ctx);
3372         struct xscale_common *xscale = target_to_xscale(target);
3373         int retval;
3374
3375         if (argc < 1)
3376         {
3377                 command_print(cmd_ctx, "usage: xscale trace_image <file> [base address] [type]");
3378                 return ERROR_OK;
3379         }
3380
3381         retval = xscale_verify_pointer(cmd_ctx, xscale);
3382         if (retval != ERROR_OK)
3383                 return retval;
3384
3385         if (xscale->trace.image)
3386         {
3387                 image_close(xscale->trace.image);
3388                 free(xscale->trace.image);
3389                 command_print(cmd_ctx, "previously loaded image found and closed");
3390         }
3391
3392         xscale->trace.image = malloc(sizeof(struct image));
3393         xscale->trace.image->base_address_set = 0;
3394         xscale->trace.image->start_address_set = 0;
3395
3396         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3397         if (argc >= 2)
3398         {
3399                 xscale->trace.image->base_address_set = 1;
3400                 COMMAND_PARSE_NUMBER(int, args[1], xscale->trace.image->base_address);
3401         }
3402         else
3403         {
3404                 xscale->trace.image->base_address_set = 0;
3405         }
3406
3407         if (image_open(xscale->trace.image, args[0], (argc >= 3) ? args[2] : NULL) != ERROR_OK)
3408         {
3409                 free(xscale->trace.image);
3410                 xscale->trace.image = NULL;
3411                 return ERROR_OK;
3412         }
3413
3414         return ERROR_OK;
3415 }
3416
3417 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3418 {
3419         struct target *target = get_current_target(cmd_ctx);
3420         struct xscale_common *xscale = target_to_xscale(target);
3421         struct xscale_trace_data *trace_data;
3422         struct fileio file;
3423         int retval;
3424
3425         retval = xscale_verify_pointer(cmd_ctx, xscale);
3426         if (retval != ERROR_OK)
3427                 return retval;
3428
3429         if (target->state != TARGET_HALTED)
3430         {
3431                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
3432                 return ERROR_OK;
3433         }
3434
3435         if (argc < 1)
3436         {
3437                 command_print(cmd_ctx, "usage: xscale dump_trace <file>");
3438                 return ERROR_OK;
3439         }
3440
3441         trace_data = xscale->trace.data;
3442
3443         if (!trace_data)
3444         {
3445                 command_print(cmd_ctx, "no trace data collected");
3446                 return ERROR_OK;
3447         }
3448
3449         if (fileio_open(&file, args[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3450         {
3451                 return ERROR_OK;
3452         }
3453
3454         while (trace_data)
3455         {
3456                 int i;
3457
3458                 fileio_write_u32(&file, trace_data->chkpt0);
3459                 fileio_write_u32(&file, trace_data->chkpt1);
3460                 fileio_write_u32(&file, trace_data->last_instruction);
3461                 fileio_write_u32(&file, trace_data->depth);
3462
3463                 for (i = 0; i < trace_data->depth; i++)
3464                         fileio_write_u32(&file, trace_data->entries[i].data | ((trace_data->entries[i].type & 0xffff) << 16));
3465
3466                 trace_data = trace_data->next;
3467         }
3468
3469         fileio_close(&file);
3470
3471         return ERROR_OK;
3472 }
3473
3474 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3475 {
3476         struct target *target = get_current_target(cmd_ctx);
3477         struct xscale_common *xscale = target_to_xscale(target);
3478         int retval;
3479
3480         retval = xscale_verify_pointer(cmd_ctx, xscale);
3481         if (retval != ERROR_OK)
3482                 return retval;
3483
3484         xscale_analyze_trace(target, cmd_ctx);
3485
3486         return ERROR_OK;
3487 }
3488
3489 COMMAND_HANDLER(xscale_handle_cp15)
3490 {
3491         struct target *target = get_current_target(cmd_ctx);
3492         struct xscale_common *xscale = target_to_xscale(target);
3493         int retval;
3494
3495         retval = xscale_verify_pointer(cmd_ctx, xscale);
3496         if (retval != ERROR_OK)
3497                 return retval;
3498
3499         if (target->state != TARGET_HALTED)
3500         {
3501                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
3502                 return ERROR_OK;
3503         }
3504         uint32_t reg_no = 0;
3505         struct reg *reg = NULL;
3506         if (argc > 0)
3507         {
3508                 COMMAND_PARSE_NUMBER(u32, args[0], reg_no);
3509                 /*translate from xscale cp15 register no to openocd register*/
3510                 switch (reg_no)
3511                 {
3512                 case 0:
3513                         reg_no = XSCALE_MAINID;
3514                         break;
3515                 case 1:
3516                         reg_no = XSCALE_CTRL;
3517                         break;
3518                 case 2:
3519                         reg_no = XSCALE_TTB;
3520                         break;
3521                 case 3:
3522                         reg_no = XSCALE_DAC;
3523                         break;
3524                 case 5:
3525                         reg_no = XSCALE_FSR;
3526                         break;
3527                 case 6:
3528                         reg_no = XSCALE_FAR;
3529                         break;
3530                 case 13:
3531                         reg_no = XSCALE_PID;
3532                         break;
3533                 case 15:
3534                         reg_no = XSCALE_CPACCESS;
3535                         break;
3536                 default:
3537                         command_print(cmd_ctx, "invalid register number");
3538                         return ERROR_INVALID_ARGUMENTS;
3539                 }
3540                 reg = &xscale->reg_cache->reg_list[reg_no];
3541
3542         }
3543         if (argc == 1)
3544         {
3545                 uint32_t value;
3546
3547                 /* read cp15 control register */
3548                 xscale_get_reg(reg);
3549                 value = buf_get_u32(reg->value, 0, 32);
3550                 command_print(cmd_ctx, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size), value);
3551         }
3552         else if (argc == 2)
3553         {
3554                 uint32_t value;
3555                 COMMAND_PARSE_NUMBER(u32, args[1], value);
3556
3557                 /* send CP write request (command 0x41) */
3558                 xscale_send_u32(target, 0x41);
3559
3560                 /* send CP register number */
3561                 xscale_send_u32(target, reg_no);
3562
3563                 /* send CP register value */
3564                 xscale_send_u32(target, value);
3565
3566                 /* execute cpwait to ensure outstanding operations complete */
3567                 xscale_send_u32(target, 0x53);
3568         }
3569         else
3570         {
3571                 command_print(cmd_ctx, "usage: cp15 [register]<, [value]>");
3572         }
3573
3574         return ERROR_OK;
3575 }
3576
3577 static int xscale_register_commands(struct command_context *cmd_ctx)
3578 {
3579         struct command *xscale_cmd;
3580
3581         xscale_cmd = register_command(cmd_ctx, NULL, "xscale", NULL, COMMAND_ANY, "xscale specific commands");
3582
3583         register_command(cmd_ctx, xscale_cmd, "debug_handler", xscale_handle_debug_handler_command, COMMAND_ANY, "'xscale debug_handler <target#> <address>' command takes two required operands");
3584         register_command(cmd_ctx, xscale_cmd, "cache_clean_address", xscale_handle_cache_clean_address_command, COMMAND_ANY, NULL);
3585
3586         register_command(cmd_ctx, xscale_cmd, "cache_info", xscale_handle_cache_info_command, COMMAND_EXEC, NULL);
3587         register_command(cmd_ctx, xscale_cmd, "mmu", xscale_handle_mmu_command, COMMAND_EXEC, "['enable'|'disable'] the MMU");
3588         register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
3589         register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
3590
3591         register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
3592         register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
3593
3594         register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
3595
3596         register_command(cmd_ctx, xscale_cmd, "dump_trace", xscale_handle_dump_trace_command, COMMAND_EXEC, "dump content of trace buffer to <file>");
3597         register_command(cmd_ctx, xscale_cmd, "analyze_trace", xscale_handle_analyze_trace_buffer_command, COMMAND_EXEC, "analyze content of trace buffer");
3598         register_command(cmd_ctx, xscale_cmd, "trace_image", xscale_handle_trace_image_command,
3599                 COMMAND_EXEC, "load image from <file> [base address]");
3600
3601         register_command(cmd_ctx, xscale_cmd, "cp15", xscale_handle_cp15, COMMAND_EXEC, "access coproc 15 <register> [value]");
3602
3603         armv4_5_register_commands(cmd_ctx);
3604
3605         return ERROR_OK;
3606 }
3607
3608 struct target_type xscale_target =
3609 {
3610         .name = "xscale",
3611
3612         .poll = xscale_poll,
3613         .arch_state = xscale_arch_state,
3614
3615         .target_request_data = NULL,
3616
3617         .halt = xscale_halt,
3618         .resume = xscale_resume,
3619         .step = xscale_step,
3620
3621         .assert_reset = xscale_assert_reset,
3622         .deassert_reset = xscale_deassert_reset,
3623         .soft_reset_halt = NULL,
3624
3625         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
3626
3627         .read_memory = xscale_read_memory,
3628         .write_memory = xscale_write_memory,
3629         .bulk_write_memory = xscale_bulk_write_memory,
3630
3631         .checksum_memory = arm_checksum_memory,
3632         .blank_check_memory = arm_blank_check_memory,
3633
3634         .run_algorithm = armv4_5_run_algorithm,
3635
3636         .add_breakpoint = xscale_add_breakpoint,
3637         .remove_breakpoint = xscale_remove_breakpoint,
3638         .add_watchpoint = xscale_add_watchpoint,
3639         .remove_watchpoint = xscale_remove_watchpoint,
3640
3641         .register_commands = xscale_register_commands,
3642         .target_create = xscale_target_create,
3643         .init_target = xscale_init_target,
3644
3645         .virt2phys = xscale_virt2phys,
3646         .mmu = xscale_mmu
3647 };