1 #use combined on interfaces or targets that can't set TRST/SRST separately
2 reset_config trst_and_srst
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
10 if { [info exists ENDIAN] } {
17 # Note above there are 2 taps
20 if { [info exists BSTAPID ] } {
23 set _BSTAPID 0x1b900f0f
25 jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
28 if { [info exists CPUTAPID ] } {
29 set _CPUTAPID $CPUTAPID
31 set _CPUTAPID 0x07926121
33 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
35 # Create the GDB Target.
36 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
37 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
38 $_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1
39 # Internal to the chip, there is 45K of SRAM
42 arm7_9 dcc_downloads enable