1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include "jtag/jtag.h"
12 #include "target/register.h"
13 #include <helper/command.h>
15 /* The register cache is statically allocated. */
16 #define RISCV_MAX_HARTS 1024
17 #define RISCV_MAX_REGISTERS 5000
18 #define RISCV_MAX_TRIGGERS 32
19 #define RISCV_MAX_HWBPS 16
21 #define DEFAULT_COMMAND_TIMEOUT_SEC 2
22 #define DEFAULT_RESET_TIMEOUT_SEC 30
24 #define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
25 #define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
26 #define RISCV_PGSHIFT 12
28 # define PG_MAX_LEVEL 4
30 #define RISCV_NUM_MEM_ACCESS_METHODS 3
32 extern struct target_type riscv011_target;
33 extern struct target_type riscv013_target;
36 * Definitions shared by code supporting all RISC-V versions.
38 typedef uint64_t riscv_reg_t;
39 typedef uint32_t riscv_insn_t;
40 typedef uint64_t riscv_addr_t;
42 enum riscv_mem_access_method {
43 RISCV_MEM_ACCESS_UNSPECIFIED,
44 RISCV_MEM_ACCESS_PROGBUF,
45 RISCV_MEM_ACCESS_SYSBUS,
46 RISCV_MEM_ACCESS_ABSTRACT
49 enum riscv_halt_reason {
51 RISCV_HALT_BREAKPOINT,
52 RISCV_HALT_SINGLESTEP,
60 struct target *target;
61 unsigned custom_number;
64 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80
65 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81
66 struct riscv_sample_buf {
76 target_addr_t address;
79 } riscv_sample_config_t;
82 struct list_head list;
90 struct command_context *cmd_ctx;
91 void *version_specific;
93 /* The hart that is currently being debugged. Note that this is
94 * different than the hartid that the RTOS is expected to use. This
95 * one will change all the time, it's more of a global argument to
96 * every function than an actual */
99 /* Single buffer that contains all register names, instead of calling
100 * malloc for each register. Needs to be freed when reg_list is freed. */
103 /* It's possible that each core has a different supported ISA set. */
106 /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
109 /* The number of triggers per hart. */
110 unsigned int trigger_count;
112 /* For each physical trigger, contains -1 if the hwbp is available, or the
113 * unique_id of the breakpoint/watchpoint that is using it.
114 * Note that in RTOS mode the triggers are the same across all harts the
115 * target controls, while otherwise only a single hart is controlled. */
116 int trigger_unique_id[RISCV_MAX_HWBPS];
118 /* The number of entries in the debug buffer. */
119 int debug_buffer_size;
121 /* This avoids invalidating the register cache too often. */
122 bool registers_initialized;
124 /* This hart contains an implicit ebreak at the end of the program buffer. */
127 bool triggers_enumerated;
129 /* Decremented every scan, and when it reaches 0 we clear the learned
130 * delays, causing them to be relearned. Used for testing. */
131 int reset_delays_wait;
133 /* This target has been prepped and is ready to step/resume. */
135 /* This target was selected using hasel. */
138 /* Helper functions that target the various RISC-V debug spec
139 * implementations. */
140 int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
141 int (*set_register)(struct target *target, int regid, uint64_t value);
142 int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
143 int (*set_register_buf)(struct target *target, int regno,
145 int (*select_current_hart)(struct target *target);
146 bool (*is_halted)(struct target *target);
147 /* Resume this target, as well as every other prepped target that can be
148 * resumed near-simultaneously. Clear the prepped flag on any target that
150 int (*resume_go)(struct target *target);
151 int (*step_current_hart)(struct target *target);
152 int (*on_halt)(struct target *target);
153 /* Get this target as ready as possible to resume, without actually
155 int (*resume_prep)(struct target *target);
156 int (*halt_prep)(struct target *target);
157 int (*halt_go)(struct target *target);
158 int (*on_step)(struct target *target);
159 enum riscv_halt_reason (*halt_reason)(struct target *target);
160 int (*write_debug_buffer)(struct target *target, unsigned index,
162 riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
163 int (*execute_debug_buffer)(struct target *target);
164 int (*dmi_write_u64_bits)(struct target *target);
165 void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
166 void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
167 void (*fill_dmi_nop_u64)(struct target *target, char *buf);
169 int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
170 int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
172 int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
173 int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
175 int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
176 uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
178 int (*sample_memory)(struct target *target,
179 struct riscv_sample_buf *buf,
180 riscv_sample_config_t *config,
183 int (*read_memory)(struct target *target, target_addr_t address,
184 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
186 /* How many harts are attached to the DM that this target is attached to? */
187 int (*hart_count)(struct target *target);
188 unsigned (*data_bits)(struct target *target);
190 COMMAND_HELPER((*print_info), struct target *target);
192 /* Storage for vector register types. */
193 struct reg_data_type_vector vector_uint8;
194 struct reg_data_type_vector vector_uint16;
195 struct reg_data_type_vector vector_uint32;
196 struct reg_data_type_vector vector_uint64;
197 struct reg_data_type_vector vector_uint128;
198 struct reg_data_type type_uint8_vector;
199 struct reg_data_type type_uint16_vector;
200 struct reg_data_type type_uint32_vector;
201 struct reg_data_type type_uint64_vector;
202 struct reg_data_type type_uint128_vector;
203 struct reg_data_type_union_field vector_fields[5];
204 struct reg_data_type_union vector_union;
205 struct reg_data_type type_vector;
207 /* Set when trigger registers are changed by the user. This indicates we eed
208 * to beware that we may hit a trigger that we didn't realize had been set. */
209 bool manual_hwbp_set;
211 /* Memory access methods to use, ordered by priority, highest to lowest. */
212 int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
214 /* Different memory regions may need different methods but single configuration is applied
215 * for all. Following flags are used to warn only once about failing memory access method. */
216 bool mem_access_progbuf_warn;
217 bool mem_access_sysbus_warn;
218 bool mem_access_abstract_warn;
220 /* In addition to the ones in the standard spec, we'll also expose additional
221 * CSRs in this list. */
222 struct list_head expose_csr;
223 /* Same, but for custom registers.
224 * Custom registers are for non-standard extensions and use abstract register numbers
225 * from range 0xc000 ... 0xffff. */
226 struct list_head expose_custom;
228 riscv_sample_config_t sample_config;
229 struct riscv_sample_buf sample_buf;
232 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
236 uint8_t tunneled_dr_width;
237 struct scan_field tunneled_dr[4];
238 } riscv_bscan_tunneled_scan_context_t;
245 unsigned vpn_shift[PG_MAX_LEVEL];
246 unsigned vpn_mask[PG_MAX_LEVEL];
247 unsigned pte_ppn_shift[PG_MAX_LEVEL];
248 unsigned pte_ppn_mask[PG_MAX_LEVEL];
249 unsigned pa_ppn_shift[PG_MAX_LEVEL];
250 unsigned pa_ppn_mask[PG_MAX_LEVEL];
253 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
254 extern int riscv_command_timeout_sec;
256 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
257 extern int riscv_reset_timeout_sec;
259 extern bool riscv_enable_virtual;
260 extern bool riscv_ebreakm;
261 extern bool riscv_ebreaks;
262 extern bool riscv_ebreaku;
264 /* Everything needs the RISC-V specific info structure, so here's a nice macro
265 * that provides that. */
266 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
267 static inline riscv_info_t *riscv_info(const struct target *target)
269 assert(target->arch_info);
270 return target->arch_info;
272 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
274 extern uint8_t ir_dtmcontrol[4];
275 extern struct scan_field select_dtmcontrol;
276 extern uint8_t ir_dbus[4];
277 extern struct scan_field select_dbus;
278 extern uint8_t ir_idcode[4];
279 extern struct scan_field select_idcode;
281 extern struct scan_field select_user4;
282 extern struct scan_field *bscan_tunneled_select_dmi;
283 extern uint32_t bscan_tunneled_select_dmi_num_fields;
284 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
285 extern int bscan_tunnel_ir_width;
286 extern bscan_tunnel_type_t bscan_tunnel_type;
288 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
289 void select_dmi_via_bscan(struct target *target);
291 /*** OpenOCD Interface */
292 int riscv_openocd_poll(struct target *target);
294 int riscv_halt(struct target *target);
297 struct target *target,
299 target_addr_t address,
300 int handle_breakpoints,
305 int riscv_openocd_step(
306 struct target *target,
308 target_addr_t address,
309 int handle_breakpoints
312 int riscv_openocd_assert_reset(struct target *target);
313 int riscv_openocd_deassert_reset(struct target *target);
315 /*** RISC-V Interface ***/
317 /* Initializes the shared RISC-V structure. */
318 void riscv_info_init(struct target *target, riscv_info_t *r);
320 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
321 * then the only hart. */
322 int riscv_step_rtos_hart(struct target *target);
324 bool riscv_supports_extension(struct target *target, char letter);
326 /* Returns XLEN for the given (or current) hart. */
327 unsigned riscv_xlen(const struct target *target);
328 int riscv_xlen_of_hart(const struct target *target);
330 /* Sets the current hart, which is the hart that will actually be used when
331 * issuing debug commands. */
332 int riscv_set_current_hartid(struct target *target, int hartid);
333 int riscv_select_current_hart(struct target *target);
334 int riscv_current_hartid(const struct target *target);
336 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
337 * without requiring multiple targets. */
339 /* Lists the number of harts in the system, which are assumed to be
340 * consecutive and start with mhartid=0. */
341 int riscv_count_harts(struct target *target);
343 /** Set register, updating the cache. */
344 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
345 /** Get register, from the cache if it's in there. */
346 int riscv_get_register(struct target *target, riscv_reg_t *value,
349 /* Checks the state of the current hart -- "is_halted" checks the actual
350 * on-device register. */
351 bool riscv_is_halted(struct target *target);
352 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
354 /* These helper functions let the generic program interface get target-specific
356 size_t riscv_debug_buffer_size(struct target *target);
358 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
359 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
360 int riscv_execute_debug_buffer(struct target *target);
362 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
363 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
364 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
365 int riscv_dmi_write_u64_bits(struct target *target);
367 /* Invalidates the register cache. */
368 void riscv_invalidate_register_cache(struct target *target);
370 int riscv_enumerate_triggers(struct target *target);
372 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
373 int riscv_remove_breakpoint(struct target *target,
374 struct breakpoint *breakpoint);
375 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
376 int riscv_remove_watchpoint(struct target *target,
377 struct watchpoint *watchpoint);
378 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
380 int riscv_init_registers(struct target *target);
382 void riscv_semihosting_init(struct target *target);
384 SEMI_NONE, /* Not halted for a semihosting call. */
385 SEMI_HANDLED, /* Call handled, and target was resumed. */
386 SEMI_WAITING, /* Call handled, target is halted waiting until we can resume. */
387 SEMI_ERROR /* Something went wrong. */
388 } semihosting_result_t;
389 semihosting_result_t riscv_semihosting(struct target *target, int *retval);
391 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
392 riscv_bscan_tunneled_scan_context_t *ctxt);
394 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
395 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);